DS101086-8

Note 16: ECLK/ERGB not used — These outputs can be disabled by setting bits 2 and 5 to “0” in the Output Enable/Polarity Control register.

“00” — Start pulse 1 clock after 1st data

“01” — Start pulse 1 clock before 1st data

“10” — Start pulse 3 clocks before 1st data

“11” — Start pulse 5 clocks before 1st data

Note 18: The Pcount and Pstart registers are programmed by 2 OCLK only in this mode. (Example) Pcount Register = “02”:4 OCLK duration

FIGURE 14. Single Port Single Bus Column Driver Interface

(SVGA Application)

DS101086-9

Note 19: Total of eight GPOs for REV, LP, and Gate Driver Control (GPO [8] dedicated to blanking function)

Note 20: GPO resolution is video clock/2

FIGURE 15. Standard or Custom Gate Driver Interface

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