FPD85310 datasheet(23/29 Pages) NSC

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Pin Description (Continued)

Pin No:

Pin Count

Pin Name

I/O

Description

COLUMN DRIVER INTERFACE

ECLK

POH

Even CD Bus Clock

ESP

POL

Even Start Pulse

ER0..ER5

POL

Even Red Bus:

EG0..EG5

POL

Even Green Bus:

EB0..EB5

POL

Even Blue Bus:

EPOL

POL

Even Polarity

OCLK

POH

Odd CD Bus Clock

OSP

POL

Odd Start Pulse

OR0..OR5

POL

Odd Red Bus:

OG0..OG5

POL

Odd Green Bus:

OB0..OB5

POL

Odd Blue Bus:

OPOL

POL

Odd Polarity

GENERAL PURPOSE OUTPUTS

GPO[8:0]

General Purpose Outputs

EEPROM INTERFACE

EE_SD

I/TO

EEPROM Serial Data

EE_SC

I/TO

EEPROM Clock

POWER SUPPLY

DDA

PLL and Bandgap Supply

GND1

PLL Ground

GNDA

Bandgap Ground

DDD

LVDS Receiver Supply

GNDD

LVDS Receiver Ground

SSIO

IO Ground

DDIO

IO Power

Digital Ground

Digital Power

TEST/CONFIGURATION

TEST[4–0]

Test/Configuration Pins.

TEST[0] — Must be “0”

TEST[1] — Must be “0”

TEST[2]

“0” —

EEPROM init values loaded every 2

frames

“1” —

EEPROM init values loaded once at

power-up

TEST[3]

“0” —

Ring Oscillator Enable

“1” —

Ring Oscillator Disable

TEST[4] — Must be “0”

•I/TO

— TTL Input/TRI-STATE® output

•TO

— TRI-STATE output

•POL — Programmable (Low Drive)

•POH — Programmable (High Drive)

•I

— TTL Input

•LVDI — Low Voltage Differential Input

•P

— Power

•G

— Ground

FPD85310 Datasheet(PDF) 23 Page - National Semiconductor (TI)

FPD85310 Datasheet(HTML) 23 Page - National Semiconductor (TI)

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