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STLUX285ATR Datasheet(PDF) 70 Page - STMicroelectronics |
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STLUX285ATR Datasheet(HTML) 70 Page - STMicroelectronics |
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70 / 126 page  Option bytes STLUX 70/126 DocID027870 Rev 1 nUBC (UBC user boot code register protection) nUBC: not (UBC) EMC byte protection. GENCFG (general configuration register) Bit 0: EN_COLD_CFG enables IC cold configuration through the option byte register AFR_IOMXP0, P1 and P2: 0: default case, the IC multifunction signal configuration is performed by the miscellaneous registers MSC_IOMXP0, MSC_IOMXP1 and MSC_IOMXP2 (warm configuration). 1: enables the multifunction signal configuration through the option byte registers AFR_IOMXP0, AFR_IOMXP1 and AFR_IOMXP2 (cold configuration). Bit 1: COMP1_2 enables the complete backward compatibility with the STLUX385 IC device. Bit 7:2: Rst_PWM [5:0] configures the PWM [n] reset value after the NRST signal 0: PWM [n] output low level (native default value) 1: PWM [n] output high level. Note: The PWM signal programmed reset value is configured during the option byte loader phase, then before the NRST is released it assumes its proper initial values. The Rst_PWM5 is not available only on the STLUX325A and must be kept 0. The Rst_PWM5 and Rst_PWM4 are not available only on the STLUX325A and must be kept 0. Table 43. nUBC (UBC user boot code register protection) Offset: 0x004802 Default value: 0xFF 7 654 32 1 0 nUBC [7:0] r/w Table 44. GENCFG (general configuration register) Offset: 0x004803 Default value: 0x00 7 6 54 32 1 0 Rst_PWM [5:0] COMP1_2(1) 1. Available only on the STLUX385A and STLUX383A, otherwise keep 0. EN_COLD_C FG r/w r/w r/w |
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