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STLUX285ATR Datasheet(PDF) 44 Page - STMicroelectronics |
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STLUX285ATR Datasheet(HTML) 44 Page - STMicroelectronics |
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44 / 126 page  I/O multifunction signal configuration STLUX 44/126 DocID027870 Rev 1 MSC_INPP2AUX1 (INPP aux register) Bit 5 - 0: INPP2_PULCTR [5:0].This register configures respectively the INPP2 [5:0] pull-up functionality as follows: 0: enable pad pull-up features (enabled by default for compatibility with the STLUX385) 1: disable pad pull-up Bit 7 - 6: RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations. Note: The MSC_IOMXP2 and MSC_INPP2AUX1 are addressable in indirect mode. On STLUX285A devices, due to DIGINs double bond interconnections the pull-up functionality must be configured in the same way for the two couple pins: DIGIN10 is controlled by register field NPP2_PULCTR[1:0]. DIGIN32 is controlled by register field INPP2_PULCTR[3:2]. DIGIN54 is controlled by register field INPP2_PULCTR[5:4]. Table 12. MSC_INPP2AUX1 (INPP aux register) Offset: 0x08 (indirect area) Default value: 0x00 7 6 5 432 1 0 RFU INPP2_PULCTR [5:0] rr/w |
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