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STLUX285ATR Datasheet(PDF) 96 Page - STMicroelectronics

No. de pieza STLUX285ATR
Descripción Electrónicos  Digital controllers for lighting and power conversion applications with up to 6 programmable PWM generators, 96 MHz PLL, DALI
PDF  126 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLUX285ATR Datasheet(HTML) 96 Page - STMicroelectronics

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Electrical characteristics
STLUX
96/126
DocID027870 Rev 1
Low power mode wake-up time
Table 76 shows the wake-up time to resume the normal operating mode from the different
low power state.
12.3.3
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 76. Wake-up times
Symbol
Parameter
Conditions
Typ.(1) Max.(1) Unit
tWU(WFI)
Wake-up
time from
wait mode to
run mode(2)
fCPU  fMASTER = 0 to 16 MHz
Ref.(3)
s
fCPU = fMASTER = 16 MHz
0.56
tWU(AH)
Wake-up
time active
halt mode to
run mode(2)
MVR voltage regulator
on(4)
Flash in operating mode(5)
HSI
(after
wake-up)
4(6)
Flash in power- down mode(5)
6(6)
MVR voltage regulator
off(4)
Flash in operating mode(5)
47(6)
Flash in power- down mode(5)
49(6)
tWU(H)
Wake-up
time from halt
mode to run
mode(2)
Flash in operating mode(5)
51
Flash in power-down mode(5)
53
1. Data based on characterization results, not tested in production.
2. Measured from the interrupt event to interrupt vector fetch.
3. tWU(WFI) = 2 x 1/fMASTER + 7 x 1/fCPU.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization (fLSI = 153.6 kHz).
Table 77. HSE user external clock characteristics
Symbol
Parameter
Conditions
Min.
Max.
Unit
fHSE_ext
User external clock source frequency
-40 °C
 TA  105 °C
0
16(1)
MHz
VHSEH(2)
HSEOSCIN input pin high level voltage
0.7 x VDD
VDD
V
VHSEL(2)
HSEOSCIN input pin low level voltage
VSS
0.3 x VDD
ILEAKHSE(2)
HSEOSCIN input pin leakage
VSS  VIN  VDD
-1
+1
µA
1. In case fHSE is configured as a direct clock for the SMED logics the maximum frequency can be 24 MHz.
2. Data based on characterization results, not tested in production.



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