SDP511 datasheet(5/10 Pages) ETC2

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Version 1.9 – July 2015

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3.4

Data transfer format

Data is transferred in byte packets in the I2C protocol,

which means in 8-bit frames. Each byte is followed by an

acknowledge bit. Data is transferred with the most

significant bit (MSB) first.

A data transfer sequence is initiated by the master

generating the Start condition (S) and sending a header

byte. The I2C header consists of the 7-bit I2C device

address and the data direction bit (R/_W).

The value of the R/_W bit in the header determines the

data direction for the rest of the data transfer sequence. If

R/_W = 0 (WRITE) the direction remains master-to-slave,

while if R/_W = 1 (READ) the direction changes to slave-

to-master after the header byte.

4. Command Set and Data Transfer

Sequences

A command is represented by an 8-bit command code.

The data direction may not change after the command

byte, since the R/_W bit of the preceding I2C header has

already determined the direction to be master-to-slave. In

order to execute commands in Read mode using I2C, the

following principle is used. On successful (acknowledged)

receipt of a command byte, the sensor stores the

command nibble internally. The Read mode of this

command is then invoked by initiating an I2C data transfer

sequence with R/_W = 1.

If a correctly addressed sensor recognizes a valid

command and access to this command is granted, it

responds by pulling down the SDA line during the

subsequent SCL pulse for the acknowledge signal (ACK).

Otherwise it leaves the SDA line unasserted (NACK).

The two most important commands are described in this

data sheet, and the data transfer sequences are specified.

Contact Sensirion for advanced sensor options.

4.1

Measurement triggering

Each individual measurement is triggered by a separate

read operation.

Note that two transfer sequences are needed to perform a

measurement. First write command byte hF1 (trigger

measurement) to the sensor, and then execute a read

operation to trigger the measurement and retrieve the flow

or differential pressure information.

On receipt of a header with R/_W=1, the sensor generates

the Hold Master condition on the bus until the first

measurement is completed. After the Hold Master

condition is released, the master can read the result as

two consecutive bytes. A CRC byte follows if the master

continues clocking the SCL line after the second result

byte. The sensor checks whether the master sends an

acknowledge after each byte and aborts the transmission

if it does not.

I2C Measurement

8-bit command code: hF1

Command: Trigger differential pressure measurement

18 19

MSByte MeasData

LSByte MeasData

14 15 16 17

23 24 25 26

Check Byte

32 33 34 35

I2CAdr

Hold Master

10 11 12 13 14 15 16 17

1 1 1 1 0 0 0 1

Command

1 0 0 0 0 0 0

I2CAdr

Hatched areas indicate that the sensor controls the SDA line.

Note that the first measurement result after reset is not

valid.

4.2

Soft reset

This command forces a sensor reset without switching the

power off and on again. On receipt of this command, the

sensor reinitializes the control/status register contents

from the EEPROM and starts operating according to these

settings.

I2C Soft Reset

8-bit command code: hFE

Command: Soft reset

system reboot

10 11 12 13 14 15 16 17

I2CAdr

1 0 0 0 0 0 0

1 1 1 1

Command

1 1 1 0

4.3

CRC-8 Redundant Data Transmission

Cyclic redundancy checking (CRC) is a popular technique

used for error detection in data transmission. The

transmitter appends an n-bit checksum to the actual data

sequence. The checksum holds redundant information

about the data sequence and allows the receiver to detect

transmission errors. The computed checksum can be

regarded as the remainder of a polynomial division, where

the dividend is the binary polynomial defined by the data

sequence and the divisor is a “generator polynomial”.

The sensor implements the CRC-8 standard based on the

generator polynomial

x8 + x5 + x4 +1.

Note that CRC protection is only used for date transmitted

from the slave to the master.

For details regarding cyclic redundancy checking, please

refer to the relevant literature.

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