34RC02 datasheet(4/16 Pages) CATALYST

4 / 16 page

CAT34RC02

Doc. No. 1052, Rev. K

FUNCTIONAL DESCRIPTION

The CAT34RC02 supports the I2C (2-wire) Bus data

transmission protocol. This Inter-Integrated Circuit Bus

protocol defines any device that sends data to the bus to

be a transmitter and any device receiving data to be a

receiver. Data transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT34RC02

operates as a Slave device. Both the Master and Slave

devices can operate as either transmitter or receiver, but

the Master alone assigns those roles. A maximum of 8

devices may be connected to the bus as determined by

the device address inputs A0, A1, and A2.

PIN DESCRIPTIONS

SCL: Serial Clock

The serial clock input pin is used to clock all data

transfers into or out of the device.

SDA: Serial Data/Address

The bidirectional serial data/address pin is used to

transfer data into and out of the device. This pin is an

open drain output in transmit mode.

A0, A1, A2: Device Address Inputs

These inputs set the device address. When left floating,

the address pins are internally pulled to ground.

WP: Write Protect

This input, when grounded or left floating, allows write

operations to the entire memory. When this pin is tied to

VCC, the entire memory is write protected.

START BIT

SDA

STOP BIT

SCL

Figure 3. Start/Stop Timing

Figure 2. Write Cycle Timing

Figure 1. Bus Timing

tWR

STOP

CONDITION

START

CONDITION

ADDRESS

ACK

8th Bit

Byte n

SCL

SDA

tHIGH

SCL

SDA IN

SDA OUT

tLOW

tBUF

tSU:STO

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

tAA

tDH

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