TNETV1644ZDU6 datasheet(92/306 Pages) TI1

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3.5 Configurations At Reset

3.5.1

Device and Peripheral Configurations at Device Reset

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Some device configurations are determined at reset. The following subsections give more details.

Table 2-5, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device

reset for configuring basic device settings for proper device operation. Table 3-12, summarizes the device

boot and configuration pins, and the device functions that they affect.

Table 3-12. Default Functions Affected by Device Boot and Configuration Pins

DEVICE BOOT AND

BOOT SELECTED

PIN MUX CONTROL

GLOBAL SETTING

PERIPHERAL SETTING

CONFIGURATION PINS

BOOTMODE[3:0]

Boot Mode

PINMUX0/PINMUX1

I/O Pin Power:

PSC/Peripherals:

Registers:

Based on

BOOTMODE[3:0], the

bootloader code programs bootloader code programs

bootloader code programs VDD3P3V_PWDN register the PSC to put

PINMUX0 and PINMUX1

to power up the I/O pins

boot-related peripheral(s)

registers to select the

required for boot.

in the Enable State, and

appropriate pin functions

programs the peripheral(s)

required for boot.

for boot operation.

FASTBOOT

Fastboot

–

Sets Device Frequency:

–

Based on BOOTMODE,

FASTBOOT, PLLMS, and

AEM the bootloader code

programs PLLC1.

AEAW[2:0]/PLLMS[2:0]

If FASTBOOT = 1 and

PINMUX0.AEAW:

Sets Device Frequency:

–

AEM = 000b, 011b, 100b

AEAW[2:0] sets the

Based on BOOTMODE,

or 101b the PLLMS[2:0]

default of this field to

FASTBOOT, PLLMS, and

selects the FASTBOOT

control the EMIFA

AEM the bootloader code

PLL Multiplier.

address bus width (only

programs PLLC1.

applicable if

PINMUX0.AEM = 001b).

Affects the pin muxing in

EMIFA/VPSS Sub-Block

AEM[2:0]

Together with FASTBOOT PINMUX0.AEM:

Sets Device Frequency:

PSC/EMIFA:

and PLLMS[2:0] ,

Sets the default of this

Based on BOOTMODE,

The EMIFA module state

determines the

field to control the EMIFA

FASTBOOT, PLLMS, and

defaults to SwRstDisable

FASTBOOT PLL

Pinout Mode.

AEM the bootloader code

if AEM = 0; otherwise, the

Multiplier.

programs PLLC1.

EMIFA module state

Affects the pin muxing in

defaults to Enable.

EMIFA/VPSS Sub-Block

0, 1, and 3.

PCIEN(1)

Host Boot:

PINMUX1.PCIEN:

–

PSC/Peripheral

PCIEN selects the type of

sets this field to control

(Applicable to Host Boot

Host Boot

the PCI pin muxing in

only):

(HPI Boot or PCI Boot)

Host Block, PCI Data

Based on the Host Boot

Block, GPIO Block,

type (PCI or HPI), the

EMIFA/VPSS Sub-Block 0

bootloader code programs

and Sub-Block 3.

the PSC to put the

(1) (2)

corresponding peripheral

in the Enable State, and

programs the peripheral

for boot operation.

(1)

Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults, except for PINMUX1.PCIEN.

(2)

In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal

pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are

disabled to be compliant to the PCI Local Bus Specification Revision 2.3.

Device Configurations

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