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3.7.1

Pin Muxing Selection At Reset

TMS320DM6437

Digital Media Processor

www.ti.com

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

This section summarizes pin mux selection at reset.

The configuration pins AEM[2:0], AEAW[2:0], and PCIEN latched at device reset determine default pin

muxing for the following Pin Mux Blocks:

• EMIFA/VPSS Block: default pin mux determined by AEM[2:0], AEAW[2:0], and PCIEN. After reset,

software may modify settings in the PINMUX0 register to add VPBE and VPFE functionalities

into this block. However, after reset, software is not allowed to modify PINMUX1.PCIEN setting

to change PCI pinout.

–

AEM[2:0] = 000b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option A is selected. This

block defaults to 61 GPIO pins.

–

AEM[2:0] = 001b, AEAW[2:0] = 000b to 100b, PCIEN = 0: Major Config Option B is selected. This

block defaults to 8-bit EMIFA (Async) Pinout Mode 1, plus 24 to 32 GPIO pins.

–

AEM[2:0] = 011b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option C is selected. This

block defaults to 8-bit EMIFA (Async) Pinout Mode 3, plus 33 GPIO pins.

–

AEM[2:0] = 100b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option D is selected. This

block defaults to 8-bit EMIFA (NAND) Pinout Mode 4, plus 47 GPIO pins.

–

AEM[2:0] = 101b, AEAW[2:0] = don't care, PCIEN = 0: Major Config Option E is selected. This

block defaults to 8-bit EMIFA (NAND) Pinout mode 5, plus 47 GPIO pins.

–

AEM[2:0] = 000b, AEAW[2:0] = don't care, PCIEN = 1: Major Config Option F is selected. This

block defaults to PCI pins, plus 45 GPIO pins.

–

AEM[2:0] = 101b, AEAW[2:0] = don't care, PCIEN = 1: Major Config Option G is selected. This

block defaults to 8-bit EMIFA (NAND) Pinout mode 5, PCI pins, plus 31 GPIO pins.

• Host Block: default pin mux determined by PCIEN.

–

PCIEN = 0: the 27 pins in Host Block default to GPIO function. Software may program

PINMUX1.HOSTBK to modify pin functions after reset.

–

PCIEN = 1: the 27 pins in Host Block serve as PCI pins. Software is not allowed to modify this

setting after reset.

• GPIO Block: pin function determined by PCIEN configuration pin.

–

PCIEN = 0: the 4 pins in GPIO Block serve as GPIO pins. Software is not allowed to modify this

setting after reset.

–

PCIEN = 1: the 4 pins in GPIO Block serve as PCI pins. Software is not allowed to modify this

setting after reset.

• PCI Data Block: pin function determined by PCIEN.

–

PCIEN = 0: the 3 pins in PCI Data Block have no function and should be left unconnected.

Software is not allowed to modify this setting after reset.

–

PCIEN = 1: the 3 pins in PCI Data Block serve as PCI pins. Software is not allowed to modify

this setting after reset.

For a description of the PINMUX0 and PINMUX1 registers and more details on pin muxing, see

Section 3.7.2.

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