ST7LITE49K2 datasheet(98/245 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7LITE49K2

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11.2.4

Low power modes

11.2.5

Interrupts

Note:

The AT4 IC is connected to an interrupt vector. The OVF event is mapped on a separate

vector (see Interrupts chapter).

They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt

mask in the CC register is reset (RIM instruction).

11.2.6

Timer control status register (ATCSR)

Reset value: 0x00 0000 (x0h)

Bit 7 = Reserved

Bit 6 = ICF Input capture flag

This Bit is set by hardware and cleared by software by reading the ATICR register (a

read access to ATICRH or ATICRL clears this flag). Writing to this bit does not change

the bit value.

0: No input capture

1: An input capture has occurred

Bit 5 = ICIE IC interrupt enable bit

This bit is set and cleared by software.

0: Input Capture Interrupt Disabled

1: Input Capture Interrupt Enabled

Table 35.

Effect of low power modes on autoreload timer

Mode

Description

Wait

No effect on AT timer

Halt

AT timer halted.

Table 36.

Description of interrupt events

Interrupt event

Event

flag

Enable

control bit

Exit from

Wait

Exit from

Halt

Exit from

Active-halt

Overflow Event

OVF1

OVIE1

Yes

AT4 IC Event

ICF

ICIE

Yes

Overflow Event2

OVF2

OVIE2

Yes

ICF

ICIE

CK1

CK0

OVF1

OVFIE1

CMPIE

Read / Write

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