ST7LITE49K2 datasheet(99/245 Pages) STMICROELECTRONICS

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ST7LITE49K2

On-chip peripherals

99/245

Bits 4:3 = CK[1:0] Counter clock selection bits

These bits are set and cleared by software and cleared by hardware after a reset. they

select the clock frequency of the counter.

Bit 2 = OVF1 Overflow flag

This bit is set by hardware and cleared by software by reading the ATCSR register. It

indicates the transition of the Counter1 CNTR1 from FFFh to ATR1 value.

0: No Counter Overflow Occurred

1: Counter Overflow Occurred

Bit 1 = OVFIE1 Overflow Interrupt Enable bit

This bit is read/write by software and cleared by hardware after a reset.

0: Overflow Interrupt Disabled.

1: Overflow Interrupt Enabled.

Bit 0 = CMPIE Compare Interrupt Enable bit

This bit is read/write by software and cleared by hardware after a reset. it can be used

to mask the interrupt generated when any of the cmpfx bit is set.

0: Output Compare Interrupt Disabled.

1: Output Compare Interrupt Enabled.

Counter register 1 high (CNTR1H)

Reset value: 0000 0000 (00h)

Counter register 1 low (CNTR1L)

Reset value: 0000 0000 (00h)

Bits 15:12 = Reserved

Table 37.

Counter clock selection

CK1

CK0

OFF

32 MHz

fLTIMER (1 ms timebase @ 8 MHz)

fCPU

000

CNTR1_

CNTR1_9

CNTR1_8

Read only

CNTR1_7

CNTR1_6

CNTR1_5

CNTR1_4

CNTR1_3

CNTR1_2

CNTR1_1

CNTR1_0

Read only

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