STM8S005C6 datasheet(74/97 Pages) STMICROELECTRONICS

74 / 97 page

Electrical characteristics

STM8S005C6 STM8S005K6

74/97

DocID022186 Rev 4

Figure 37. Recommended reset pin protection

9.3.8

SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under ambient temperature, fMASTER frequency and VDD supply voltage

conditions. tMASTER = 1/fMASTER.

Refer to I/O port characteristics for more details on the input/output alternate function

characteristics (NSS, SCK, MOSI, MISO).

0.1µF

External

reset

circuit

STM8

Filter

RPU

VDD

Internal reset

NRST

(optional)

Table 41. SPI characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI clock rise and fall time

Capacitive load: C = 30 pF

tsu(NSS)

(1)

NSS setup time

Slave mode

4 x tMASTER

th(NSS)

(1)

NSS hold time

Slave mode

tw(SCKH)

(1)

tw(SCKL)

(1)

SCK high and low time

Master mode

tSCK/2 - 15

tSCK/2 + 15

tsu(MI)

(1)

tsu(SI)

(1)

Data input setup time

Master mode

Slave mode

th(MI)

(1)

th(SI)

(1)

Data input hold time

Master mode

Slave mode

ta(SO)

(1)(2)

Data output access time

Slave mode

3 x tMASTER

tdis(SO)

(1)(3)

Data output disable time

Slave mode

tv(SO)

(1)

Data output valid time

Slave mode (after enable edge)

tv(MO)

(1)

Data output valid time

Master mode (after enable edge)

th(SO)

(1)

Data output hold time

Slave mode (after enable edge)

th(MO)

(1)

Master mode (after enable edge)

Values based on design simulation and/or characterization results, and not tested in production.

Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.

Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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