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STR710FZ2 Datasheet(PDF) 46 Page - STMicroelectronics |
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STR710FZ2 Datasheet(HTML) 46 Page - STMicroelectronics |
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46 / 80 page  Electrical parameters STR71xFxx STR710RZ 46/80 Doc ID 10350 Rev 13 ΔtJITTER1 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Table 20. PLL2 characteristics Symbol Parameter Test conditions Value Unit Min Typ Max fPLLCLK2 PLL multiplier output clock 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 μs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 μs ΔtJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Table 21. Low-power mode wakeup timing Symbol Parameter Typ Unit tWULPWFI Wakeup from LPWFI mode 26(1) 1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down µs tWUSTOP Wakeup from STOP mode 2048 CLK Cycles (2) 2. The CLK clock is derived from the external oscillator. tWUSTBY Wakeup from STANDBY mode 2048 CLK Cycles + 8 CLK2 Cycles(3) 3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084) Cycles Table 19. PLL1 characteristics (continued) Symbol Parameter Test conditions Value Unit Min Typ Max |
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