| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
WM8775EDS/R Datasheet(PDF) 16 Page - Wolfson Microelectronics plc |
|
|
|||||||||||||||||||||||||||||
WM8775EDS/R Datasheet(HTML) 16 Page - Wolfson Microelectronics plc |
|
16 / 36 page ![]() WM8775 Product Preview w PP Rev 1.8, June 2004 16 AUDIO INTERFACE FORMATS Audio data output from the ADC filters, via the Digital Audio Interface. 5 popular interface formats are supported: • Left Justified mode • Right Justified mode • I 2S mode • DSP Early mode • DSP Late mode All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I 2S modes, the digital audio interface outputs ADC data on DOUT. Audio Data for each stereo channel is time multiplexed with ADCLRC indicating whether the left or right channel is present. ADCLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I 2S modes, the minimum number of BCLKs per ADCLRC period is 2 times the selected word length. ADCLRC must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on ADCLRC is acceptable provided the above requirements are met. In DSP early or DSP late mode, the ADC data may also be output, with ADCLRC used as a frame sync to identify the MSB of the first word. The minimum number of BCLKs per ADCLRC period is 2 times the selected word length LEFT JUSTIFIED MODE In left justified mode, the MSB of the ADC data is output on DOUT and changes on the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK. ADCLRC is high during the left samples and low during the right samples (Figure 12). LEFT CHANNEL RIGHT CHANNEL ADCLRC BCLK DOUT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB Figure 12 Left Justified Mode Timing Diagram RIGHT JUSTIFIED MODE In right justified mode, the LSB of the ADC data is output on DOUT and changes on the falling edge of BCLK preceding a ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is high during the left samples and low during the right samples (Figure 13). |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |