WM8775EDSSLASHR datasheet(29/36 Pages) WOLFSON

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WM8775

PP Rev 1.8, June 2004

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

0000111

Timeout Clock

Disable

TOD

ADC Analogue PGA Zero cross detect timeout disable

0 : Timeout enabled

1: Timeout disabled

1:0

ADCFMT[1:0]

Interface format select

00: right justified mode

01: left justified mode

10: I

2S mode

11: DSP mode

ADCLRC Polarity or DSP Early/Late mode select

ADCLRP

In left/right/ I

2S modes:

ADCLRC Polarity (normal)

0 : normal ADCLRC polarity

1: inverted ADCLRC polarity

DSP Mode

0: Early DSP mode

1: Late DSP mode

ADCBCP

BITCLK Polarity

0: Normal - ADCLRC sampled on rising edge of BCLK;

DOUT changes on falling edge of BCLK.

1: Inverted - ADCLRC sampled on falling edge of BCLK;

DOUT changes on rising edge of BCLK.

5:4

ADCWL[1:0]

Input Word Length

00: 16-bit Mode

01: 20-bit Mode

10: 24-bit Mode

11: 32-bit Mode (not supported in right justified mode)

ADCMCLK

ADCMCLK Polarity

0 : non-inverted

1: inverted

R11 (0Bh)

0001011

Interface

Control

ADCHPD

ADC High pass Filter Disable:

0: High pass Filter enabled

1: High pass Filter disabled

2:0

ADCRATE[2:0]

010

Master Mode MCLK:ADCLRC ratio select:

010: 256fs

011: 384fs

100: 512fs

101: 768fs

ADCOSR

ADC oversample rate select

0: 128x oversampling

1: 64x oversampling

12 (0Ch)

0001100

Master Mode

Control

ADCMS

Maser/Slave interface mode select

0: Slave Mode – ADCLRC and BCLK are inputs

1: Master Mode – ADCLRC and BCLK are outputs

PWDN

Chip Powerdown Control (works together with ADCD):

0: All circuits running, outputs are active

1: All circuits in power save mode, outputs muted

ADCPD

ADC powerdown:

0: ADC enabled

1: ADC disabled

R13 (0Dh)

0001101

Powerdown

Control

AINPD

Input mux and buffer powerdown

0: Input mux and buffer enabled

1: Input mux and buffer powered down

WM8775EDS/R Datasheet(PDF) 29 Page - Wolfson Microelectronics plc

WM8775EDS/R Datasheet(HTML) 29 Page - Wolfson Microelectronics plc

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