AM652X datasheet(153/299 Pages) TI1

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AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Specifications

Table 5-27. System Clocks Operating Frequency Range (continued)

System Clocks (1)

Bypass Min

(MHz)

Bypass Max

(MHz)

Minimum Operating Frequency

(MHz)

PLL1 (PER0 PLL)

PLL2 (PER1 PLL)

PLL3 (DDR PLL)

PLL4 (DSS PLL)

PLL6 (ARM0 PLL)

PLL7 (ARM1 PLL)

MCU_PLL0

MCU_PLL1

(1) Supported input reference clock frequencies to the PLL are 19.2/24/25/26 MHz only.

(2) Interconnect clock on DSS is CPU/4. This will range from 100 MHz to 250 MHz.

(3) When Main PLL is configured to 400 MHz mode, DSS can only support a Max Pixel clock of 74.25 MHz. For lower resolution Displays

the DSS clock can be lower than 74.25 MHz.

5.11.4.5 Device Inputs and Outputs Module Clocks Frequencies

NOTE

NOTE TO USERS:

The content of this section is UNDER DEVELOPMENT!

5.11.4.6 Recommended Clock and Control Signal Transition Behavior

All clocks and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner. Monotonic transitions are more easily ensured with faster switching signals. Slower input

transitions are more susceptible to glitches due to noise, and special care must be taken for slow input

clocks.

5.11.4.7 Interface Clock Specifications

5.11.4.7.1 Interface Clock Terminology

The interface clock is used at the system level to sequence the data and to control transfers accordingly

with the interface protocol.

5.11.4.7.2 Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

•

The maximum operating frequency

The interface clock frequency documented here is the maximum clock frequency, which corresponds to

the maximum frequency programmable on this output clock. This frequency defines the maximum limit

supported by the Device IC and does not take into account any system consideration (PCB, peripherals).

The system designer must take into account these system considerations and the Device IC timing

characteristics to properly define the maximum operating frequency that corresponds to the maximum

frequency supported to transfer the data on this interface.

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