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AM652X Datasheet(PDF) 155 Page - Texas Instruments

No. de pieza AM652X
Descripción Electrónicos  Sitara Processors
PDF  299 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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AM652X Datasheet(HTML) 155 Page - Texas Instruments

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RMII[x]_REFCLK
(input)
RMII2
RMII3
RMII1
MDIO3
MDIO1
MDIO2
MDIO7
MDIO4
MDIO5
MDIO6
MDIO6
MDIO_CLK
MDIO_DATA
(input)
MDIO_DATA
(output)
SPRS8xx_GMAC_MDIO_07
155
AM6548, AM6528, AM6546
AM6526, AM6527
www.ti.com
SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018
Submit Documentation Feedback
Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO.
PARAMETER
MIN
MAX
UNIT
MDIO3
tc(MDC)
Cycle time, MDIO_CLK
400
ns
MDIO4
tw(MDCH)
Pulse Duration, MDIO_CLK high
160
ns
MDIO5
tw(MDCL)
Pulse Duration, MDIO_CLK low
160
ns
MDIO6
tt(MDC)
Transition time, MDIO_CLK
5
ns
MDIO7
td(MDC_MDIO)
Delay time, MDIO_CLK High to MDIO_DATA valid
10
390
ns
Figure 5-28. CPSW2G MDIO diagrams receive and transmit
5.11.5.2.2 CPSW2G RMII Timings
Table 5-31, Table 5-32, and Figure 5-29 present timing requirements for CPSW2G RMII receive.
Table 5-31. Timing Requirements for RMII[x]_REFCLK - RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
RMII1
tc(REF_CLK)
Cycle time, REF_CLK
19.999
20.001
ns
RMII2
tw(REF_CLKH)
Pulse Duration, REF_CLK High
7
13
ns
RMII3
tw(REF_CLKL)
Pulse Duration, REF_CLK Low
7
13
ns
Figure 5-29. RMII[x]_REFCLK Timing - RMII Mode
Table 5-32. Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
NO.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
RMII4
tsu(RXD-REF_CLK)
Setup time, RXD[1:0] valid before REF_CLK
4
ns
tsu(CRS_DV-REF_CLK)
Setup time, CRS_DV valid before REF_CLK
4
ns
tsu(RX_ER-REF_CLK)
Setup time, RX_ER valid before REF_CLK
4
ns



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