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AM652X Datasheet(PDF) 162 Page - Texas Instruments |
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AM652X Datasheet(HTML) 162 Page - Texas Instruments |
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162 / 299 page  EPWM_SOCA/B PWM5 EPERIPHERALS_TIMNG_04 EPWM_SYNCO PWM2 EPWM_A/B_out PWM1 PWM1 APWM CAP2 EPERIPHERALS_TIMNG_02 162 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated (1) P = sysclk Figure 5-37. eCAP Output Timings 5.11.5.7 eHRPWM The supported features by the device eHRPWM are: • Dedicated 16-bit time-base counter with period and frequency control • Two independent PWM outputs which can be used in different configurations (with single-edge operation, with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation) • Asynchronous override control of PWM signals during fault conditions • Programmable phase-control support for lag or lead operation relative to other EPWM modules • Dead-band generation with independent rising and falling edge delay control • Programmable trip zone allocation of both latched and un-latched fault conditions • Events enabling to trigger both CPU interrupts and start of ADC conversions Table 5-42, Table 5-43 and present timing and switching characteristics for eHRPWM (see Figure 5-38, Figure 5-39, Figure 5-40, and Figure 5-41). Table 5-42. Timing Requirements for eHRPWM NO. PARAMETER DESCRIPTION MIN MAX UNIT PWM1 tw(PWM) Pulse duration, PWM output high/low -3 + 1P(1) ns PWM2 tw(SYNCOUT) Pulse duration, Sync output -3 + 1P(1) ns PWM3 td(TZ-PWM) Delay time, trip input active to PWM forced high/low 10 ns PWM4 td(TZ-PWMZ) Delay time, trip input active to PWM Hi-Z 10 ns PWM5 tw(SOC) Pulse duration, SOC output (asynchronous) -3 + 1P(1) ns (1) P = sysclk Figure 5-38. ePWM_A/B_out, ePWM_SYNCO, and ePWM_SOCA/B Input Timings |
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