AM652X datasheet(165/299 Pages) TI1

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165

AM6548, AM6528, AM6546

AM6526, AM6527

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SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

(1) P = functional clock period in ns.

Table 5-47. GPIO Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

GP1

tw(GPIO_OUT)

Minimum Output Pulse Width

-4.6 +

0.975P(1)

(1) P = functional clock period in ns.

For more information, see section General-Purpose Interface (GPIO) in chapter Peripherals of the device

TRM.

5.11.5.10 GPMC

For more details about features and additional description information on the device General-Purpose

Memory Controller, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6,

Detailed Description.

5.11.5.10.1 GPMC and NOR Flash—Synchronous Mode

Table 5-48 and Table 5-49 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 5-43 through Figure 5-47).

Table 5-48. GPMC and NOR Flash Timing Requirements—Synchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE(3)

MIN

MAX

UNIT

F12

tsu(dV-clkH)

Setup time, input data GPMC_AD[15:0] valid

before output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

0.59

not_div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

0.34

F13

th(clkH-dV)

Hold time, input data GPMC_AD[15:0] valid after

output clock GPMC_CLK high

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

1.78

not_div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

1.78

F21

tsu(waitV-clkH)

Setup time, input wait GPMC_WAIT[x] valid before

output clock GPMC_CLK high (1)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

0.59

not_div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

0.34

F22

th(clkH-waitV)

Hold time, input wait GPMC_WAIT[x] valid after

output clock GPMC_CLK high (1)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

1.78

not_div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

1.78

(1) In GPMC_WAIT[x], x is equal to 0 or 1.

(2) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-

Purpose Memory Controller section in the Device TRM.

(3) For div_by_1_mode:

–

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:

–

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:

–

GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX_100:

–

gpmc_fclk_sel[1:0] = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

AM652X Datasheet(PDF) 165 Page - Texas Instruments

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