AM652X datasheet(166/299 Pages) TI1

166 / 299 page

166

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Specifications

For TIMEPARAGRANULARITY_X1:

–

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME,

RD/WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

Table 5-49. GPMC and NOR Flash Switching Characteristics—Synchronous Mode(2)

NO.

PARAMETER

DESCRIPTION

MODE(20)

MIN

MAX

UNIT

1 / tc(clk)

Period, output clock GPMC_CLK (18)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

tw(clkH)

Typical pulse duration, output clock GPMC_CLK

high

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-0.3+0.

475*P

(15)

tw(clkL)

Typical pulse duration, output clock GPMC_CLK

low

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-0.3+0.

475*P

(15)

tdc(clk)

Duty cycle error, output clock GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-500

500

tJ(clk)

Jitter standard deviation, output clock GPMC_CLK

(19)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

33.33

tR(clk)

Rise time, output clock GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

tF(clk)

Fall time, output clock GPMC_CLK

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

tR(do)

Rise time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

tF(do)

Fall time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

td(clkH-csnV)

Delay time, output clock GPMC_CLK rising edge

to output chip select GPMC_CSn[x] transition (14)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+F

(6)

4.5+F (6)

td(clkH-csnIV)

Delay time, output clock GPMC_CLK rising edge

to output chip select GPMC_CSn[x] invalid (14)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1;

no extra_delay

-2.2+E

(5)

4.5+E (5)

td(aV-clk)

Delay time, output address GPMC_A[27:1] valid to

output clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

4.5+B (2)

td(clkH-aIV)

Delay time, output clock GPMC_CLK rising edge

to output address GPMC_A[27:1] invalid

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3

4.5

td(be[x]nV-clk)

Delay time, output lower byte enable and

command latch enable GPMC_BE0n_CLE, output

upper byte enable GPMC_BE1n valid to output

clock GPMC_CLK first edge

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+B

(2)

1.9+B (2)

td(clkH-be[x]nIV)

Delay time, output clock GPMC_CLK rising edge

to output lower byte enable and command latch

enable GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n invalid (11)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D (4)

td(clkL-be[x]nIV)

Delay time, GPMC_CLK falling edge to

GPMC_BE0n_CLE, GPMC_BE1n invalid (12)

div_by_1_mode;

GPMC_FCLK_MUX_100;

TIMEPARAGRANULARITY_X1

-2.3+D

(4)

1.9+D (4)

AM652X Datasheet(PDF) 166 Page - Texas Instruments

AM652X Datasheet(HTML) 166 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL