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GD5F1GQ4REFJS Datasheet(PDF) 19 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F1GQ4REFJS Datasheet(HTML) 19 Page - GigaDevice Semiconductor (Beijing) Inc. |
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19 / 60 page ![]() SPI(x1/x2/x4) NAND Flash 1G 19 8.5 Read From Cache x4 (6BH) The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. Figure8-4. Read From Cache x4 Sequence Diagram SO(SIO1) High-Z 26 27 28 29 25 1 5 1 5 1 5 1 30 31 Byte1 24 34 35 36 37 33 38 39 32 5 Dummy Byte 0 4 0 4 0 4 0 4 4 5 WP#(SIO2) High-Z HOLD#(SIO3) High-Z CS# SCLK SI(SIO0) SO(SIO1) WP#(SIO2) HOLD#(SIO3) 2 6 2 6 2 6 2 6 6 3 7 3 7 3 7 3 7 7 Byte2 Byte3 Byte4 Command 0 1 2 3 4 5 6 7 6BH CS# SCLK SI(SIO0) 8 9 10 11 12 13 14 22 23 3 2 1 0 0 0 A11-0 0 0 11 10 dummy<3:0> 6 5 4 3 2 1 0 7 |
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