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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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GD5F1GQ4REFJS Datasheet(PDF) 40 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD5F1GQ4REFJS Datasheet(HTML) 40 Page - GigaDevice Semiconductor (Beijing) Inc. |
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40 / 60 page  SPI(x1/x2/x4) NAND Flash 1G 40 12.2.2 Hardware RESET Setting a) 8-pin package For the 8-pin package, RESET#, HOLD# and data IO3 share the same pin7. The pin7 can be configured as any of the three functions depending on the status register setting. When QE=0, HOLDB/RST=1, the pin7 acts as a RESET# pin. When QE=1 or QE=0 HOLDB/RST=0, the pin7 will be configured as the other functions and Hardware Reset function can’t be used. QE and HOLDB/RST registers can be set by Set Feature command (see table12-2). QE can be set by Set Feature command when address is B0H and HOLDB/RST can be set by Set Feature command when address is D0H. Both of them can be read out by Get Feature command with related address. Through reading the status registers, users could know the value and infer which function is supported on the pin7. By default QE and HOLDB/RST registers are both 0 after power-on-reset or hardware reset. Table12-2. Features Settings Register Addr. 7 6 5 4 3 2 1 0 Protection A0H BRWD Reserved BP2 BP1 BP0 INV CMP Reserved Feature B0H OTP_PRT OTP_EN Reserved ECC_EN Reserved Reserved Reserved QE Status C0H Reserved Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP Feature D0H HOLDB/RST DS_S1 DS_S0 Reserved Reserved Reserved Reserved Reserved Status F0H Reserved Reserved ECCSE1 ECCSE0 Reserved Reserved Reserved Reserved b) 16-pin/24-pin package For 16-pin/24-pin package (see Figure2-1), a dedicated RESET# pin is provided and it is independent of QE bit setting. At the same time, HOLDB/RST register is not existed in 16-pin/24-pin package, and the corresponding bit in command Set/Get Feature with address D0H is reserved. Table12-3. Features Settings Register Addr. 7 6 5 4 3 2 1 0 Protection A0H BRWD Reserved BP2 BP1 BP0 INV CMP Reserved Feature B0H OTP_PRT OTP_EN Reserved ECC_EN Reserved Reserved Reserved QE Status C0H Reserved Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP Feature D0H Reserved DS_S1 DS_S0 Reserved Reserved Reserved Reserved Reserved Status F0H Reserved Reserved ECCSE1 ECCSE0 Reserved Reserved Reserved Reserved |
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