STR720 datasheet(370/401 Pages) STMICROELECTRONICS

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STR720 - SYSTEM RESET

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26 SYSTEM RESET

26.1 RESET Input Pin

This pin is used to force a system reset which initializes the device in a predefined state.

Activating this pin does not affect in any way the operation of either Real-Time-Clock or

on-chip emulation and debug sections, which are independently initialized by dedicated pins.

To improve the noise immunity of the device, the RESET input pin (RSTIN) has a Schmitt

trigger input circuit with hysteresis and an on-chip RC filter is implemented. The filter is sized

to filter out all spikes shorter than 50 ns. On the other hand, it is recommended to provide valid

pulse on RSTIN with a duration of at least 500 ns to be sure that the asynchronous pulse is

properly latched by system. This means that all the pulses whose length is between 50 ns and

500 ns can either be filtered or recognized as valid, depending on the operating conditions

and process variations. As a recommendation, the power-up RSTIN pulse should last for

about 200

µs in order to be sure that the internal current references used to supply the clock

input pad are already settled to their nominal value.

Figure 68. Recommended Signal to be applied on RSTIN pin

26.2 RTCRST Input Pin

This pin is used to initialize Real-Time-Clock section independently from the rest of the

system. To improve the noise immunity of this critical input pin, RTCRST has a Schmitt trigger

input circuit with hysteresis and an on-chip RC filter is implemented, similar to the one

described for RESET input pin. The filter is sized to filter out all spikes shorter than 50 ns and

minimum RTCRST pulse duration is recommended to be longer than 500 ns. This means that

all the pulses whose length is between 50 ns and 500 ns can either be filtered or recognized

valid,

depending

the

operating

conditions

and

process

variations.

recommendation, the power-up RTCRST pulse should last for about 1 s in order to be sure

that 32 kHz oscillator is has completed its start-up phase and settled to its nominal oscillation

frequency and amplitude.

VRSTIN

0.3 VDD

0.7 VDD

VDD

500 ns Minimum (200

µs power-up)

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