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STR720 Datasheet(PDF) 371 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 371 Page - STMicroelectronics |
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371 / 401 page ![]() STR720 - SYSTEM RESET 371/401 26.3 JTRST Input Pin This pin is used to initialize on-chip emulation and debug logic independently from the rest of the system. To improve the noise immunity of this critical input pin, JTRST has a Schmitt trigger input circuit with hysteresis and an on-chip RC filter is implemented, similar to the one described for RESET input pin. The filter is sized to filter out all spikes shorter than 50 ns and minimum JTRST pulse duration is recommended to be longer than 500 ns. This means that all the pulses whose length is between 50 ns and 500 ns can either be filtered or recognized as valid, depending on the operating conditions and process variations. 26.4 Power-on/off and Stand-by entry/exit At power-on or Stand-by exit, it is recommended to held low RSTIN pin to guarantee a proper initialization of STR720 system and avoid malfunctions of the RTC logic. In particular, when VDD and VDD3 are still too low to allow the internal logic to work properly, the system must be mantained under reset status, forcing a HW Reset through the RSTIN pin. In this way the system sees a HW Reset and the flag register (CLK_FLAG in RCCU module) assumes the corresponding configuration (all Reset flags cleared). To avoid unpredictable current injection and power consumption, it is recommended to have the VDD3 value always greater than VDD during the power-on phase, as illustrated in next Figure 69 on page 371. The distinction between power-on reset and hardware system reset consists in the fact that typical hardware reset sequences do not affect Real-Time-Clock section, leaving RTC running while rest of the system is restarted. This happens also when system enters and exit stand-by mode. On the contrary a power-on reset will see both system and RTC section being initialized. In order to distinguish between a power-on reset and a hardware system reset (or Figure 69. Power-on supply sequence VDD3 VDD RSTIN Reset pin driven low |
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