STPMIC1APQR datasheet(34/140 Pages) STMICROELECTRONICS

No. de pieza	STPMIC1APQR

Descripción Electrónicos	Highly integrated power management IC for micro processor units

PDF	140 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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34 / 140 page

Figure 42. PWM clock generation

Clock synchronization (HP mode)– buck controller integrates phase locked loop (PLL) circuit, that maintains

steady-state frequency in CCM phase-locked to reference 2 MHz clock generated by internal oscillator. Each

buck has its own reference clock that is shifted from master clock by 90 degree, which minimizes the chance of

multiple controllers switching at the same time, and improving EMI performance. Refer to Figure 43. PWM clock

synchronisation .

Figure 43. PWM clock synchronisation

Voltage accuracy (HP mode)- COT controllers are well-known for their excellent transient response but standard

implementations usually suffer from a high output load regulation error. To cope with this problem, the STPMIC1

adaptive COT controller also integrates an ACCU loop circuit that fixes the parameters of controller in order to

reach the maximum possible accuracy of output voltage for all operating conditions. Refer to Figure 44. Buck

block diagram.

STPMIC1

Buck converters

DS12792 - Rev 7

page 34/140

STPMIC1APQR Datasheet(PDF) 34 Page - STMicroelectronics