AD9546SLASHPCBZ datasheet(181/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 181 of 205

When the start-up conditions select the serial port to be I2C

mode (that is, M4 is Logic 1 at startup), the SDO/M5 and

CSB/M6 pins determine the I2C port device address offset, per

Table 103. The logic levels in Table 103 only apply during a

power-up or reset operation.

Table 103. I²C Device Address Offset

CSB/M6

SDO/M5

Address Offset

Not applicable

1001000 (0x48)

1001001 (0x49)

1001010 (0x4A)

1001011 (0x4B)

X means don’t care.

DEFINING AN Mx PIN FOR STATUS OR CONTROL

To define an Mx pin as a status or control pin, use Bit 7 in the

Logic 0 (default) defines the associated Mx pin as a control pin,

whereas Logic 1 defines the associated Mx pin as a status pin.

Table 104. Mx Pin Mode Register Addresses

Mx Pin

0x0102

0x0103

0x0104

0x0105

0x0106

SDO/M5

0x0107

CSB/M6

0x0108

The status or control function for an Mx pin depends on an

8-bit code stored in the Mx pin function register addresses

associated with a specific Mx pin per Table 105.

Because the Mx pin mode and code reside in different registers,

the following programming procedure is necessary. First, write

the desired mode via Bit 7 of the appropriate mode register (see

Table 104) with Bits[6:0] = 0. Then, write the desired code to

the corresponding code register (see Table 105). Finally, assert

an IO update. When programming more than one Mx pin, it is

acceptable to wait until all the desired Mx pin mode and code

registers are programmed before asserting an IO update.

Table 105. Mx Pin Status or Control Code Register Addresses

Mx Pin

0x0182

0x0183

0x0184

0x0185

0x0186

SDO/M5

0x0187

CSB/M6

0x0188

A 2-bit modifier augments the status or control functionality of

an Mx pin. Each Mx pin has a dedicated modifier bit pair per

Table 106. The modifier bits affect the associated Mx pin

differently depending on the Mx pin operating mode: status or

control. The specific meaning of the 2-bit code appears in

Table 107 for status functions and in Table 108 for control

functions.

Table 106. Modifier Bits of Mx Pin Functionality

[D7:D6]

[D5:D4]

[D3:D2]

[D1:D0]

0x0100

0x0101

Unused

STATUS FUNCTIONALITY

Configuring an Mx pin for status functionality gives the user

access to specific internal device status and IRQ functions in

the form of a hardware pin that produces a logic signal.

The drive strength of an Mx pin when configured for status

functionality is programmable via Bits[6:0] of Register 0x0109,

where Bits[6:0] correspond to M6 to M0, respectively). Logic 0

(default) selects normal drive strength (~6 mA) and Logic 1

selects weak drive strength (~3 mA).

When configured as a status pin, the modifier bits affect the status

functionality per Table 107. The PMOS open-drain mode requires

an external pull-down resistor. The NMOS open-drain mode

requires an external pull-up resistor. The open-drain modes enable

the implementation of wire-OR’ed functionality of multiple Mx

status pins (including Mx status pins across multiple AD9546

devices or other compatible devices—for example, to implement

an IRQ bus).

Table 107. Mx Status Pin 2-Bit Modifier Codes from Table 106

Code

Mode

Description

CMOS,

active high

Default. Output is Logic 0 for a deasserted

internal function and Logic 1 for an

asserted internal function.

CMOS,

active low

Output is Logic 1 for deasserted internal

function and Logic 0 for an asserted

internal function.

PMOS,

open drain

Output is high impedance for a deasserted

internal function and active high for an

asserted internal function.

NMOS,

open drain

Output is high impedance for a deasserted

internal function and active low for an

asserted internal function.

AD9546/PCBZ Datasheet(PDF) 181 Page - Analog Devices

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