AD9546SLASHPCBZ datasheet(179/205 Pages) AD

179 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 179 of 205

The value of the 3-bit bit field for a given destination establishes

the COMPx factor applied to that destination (see the

Integrated Compensation Subsystem section for details).

The compensation methods relate to columns in the bit field

matrix of Figure 121, whereas the compensation destinations

relate to rows. Organizing the compensation bit field matrix in

this way enables any compensation destination to receive any

one of the eight possible COMPx signals (see Figure 120).

Certain compensation destinations have constraints on which

compensation methods apply (see the Compensation

Assignment Guidelines section).

For example, to provide system clock compensation to

Auxiliary NCO 0 using a combination of Compensation

Method 1 and Compensation Method 3, follow these steps:

1. Determine the appropriate compensation destination bit

field per Figure 121. In this case, Bits[2:0] of

destination is auxiliary NCO 0.

2. Determine the 3-bit code to write to Bits[2:0] of

corresponding to the appropriate COMPx. In this case, the

code is 5 (101 binary) because it uses CF1 and CF3 per the

middle column of Table 100. In conclusion, by programming

Bits[2:0] = 5 in Register 0x0281, auxiliary NCO 0 receives

both Compensation Method 1 and Compensation Method 3.

NOT USED

AUXILIARY DPLL NCO

COMPENSATION

DESTINATION

REFx AND AUXILIARY REFx TDC

COMPENSATION DESTINATION

AUXILIARY NCO 1

COMPENSATION DESTINATION

AUXILIARY NCO 0

COMPENSATION DESTINATION

DPLL1 NCO

COMPENSATION DESTINATION

DPLL0 NCO

COMPENSATION DESTINATION

DATA

BITS

0x0280

0x0281

0x0282

CF3

NOT USED

CF2

CF1

CF3

CF2

CF1

Figure 121. System Clock Compensation Registers

AD9546/PCBZ Datasheet(PDF) 179 Page - Analog Devices

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