AD9546SLASHPCBZ datasheet(177/205 Pages) AD

177 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 177 of 205

Auxiliary DPLL Lock Detector

The auxiliary DPLL has a built in lock detector for indicating

lock status. The lock and unlock thresholds for the lock

detector are fixed and not user programmable.

The auxiliary DPLL lock detector status is available in real time

via status Bit 1 (auxiliary DPLL lock status) of Register 0x3002.

The auxiliary DPLL lock and unlock states are Logic 1 and

Logic 0, respectively.

The auxiliary DPLL lock detector status is also available via the

IRQ mechanism (see the Interrupt Request (IRQ) section) by

means of Bit 0 and Bit 1 of Register 0x300C. Bit 0 and Bit 1

provide latched information regarding state transitions of the

auxiliary DPLL lock status bit. Bit 0 latches to Logic 1 when the

auxiliary DPLL lock status bit transitions from Logic 0 to Logic

1, whereas Bit 1 latches to Logic 1 when the auxiliary DPLL lock

status bit transitions from Logic 1 to Logic 0.

Because Bit 0 and Bit 1 represent the latched state transitions of

the auxiliary DPLL lock status bit, they may represent a

condition that is no longer true. Therefore, the user must clear

Bit 0 and Bit 1 via Bit 0 and Bit 1, respectively, of Register

0x2007. Otherwise, the user may lose indication of subsequent

state changes of the auxiliary DPLL lock status bit.

Auxiliary DPLL Holdover

Under normal conditions, the auxiliary DPLL continuously

updates CF3 computations with each rising edge event to the

TDC associated with the stable reference. Under certain

conditions, however, the auxiliary DPLL can enter a holdover

state. For example,



The user programs auxiliary DPLL bandwidth = 0



The reference monitor indicates a fault

While in the holdover state, the auxiliary DPLL is effectively in

an open-loop condition (that is, the NCO output is static). As

such, the auxiliary DPLL holds the CF3 value that existed just

prior to entering the holdover state. Therefore, it is not possible

to ascertain further stability information until the loop resumes

normal operation. When the condition that forced holdover no

longer exists, however, the auxiliary DPLL returns to closed-

loop operation and resumes updating CF3 (that is, when the

lock detector indicates a lock condition).

INTEGRATED COMPENSATION SUBSYSTEM

The three compensation methods comprise the integrated

compensation subsystem of the AD9546. The compensation

subsystem allows the user to employ any combination of the

three compensation methods to any of the NCOs and TDCs

within the AD9546 (barring a few exceptions per the

Compensation Assignment Guidelines section). Figure 120

shows a simplified block diagram of the compensation

subsystem.

In Figure 120, note the implied feedback path between

DPLL0/DPLL1 and Compensation Method 2 and between the

auxiliary DPLL and Compensation Method 3. The reason for

the implied feedback is that the indicated compensation

destination (the auxiliary DPLL, for example) can receive

compensation from any of the compensation sources via the

combiner and distributor. Thus, the compensation destination

can potentially apply self compensation, which leads to an

undesired positive feedback loop. The user must avoid such

loops (see the Compensation Assignment Guidelines section).

For digitized clocking applications (see the Digitized Clocking

section), the common clock DPLL replaces the auxiliary DPLL.

Thus, in a digitized clocking application, CF3 originates from

the common clock DPLL. The implication is that, when

applying system clock compensation in a digitized clocking

application, the burden of stability falls on the common clock

reference to the common clock DPLL.

COMPENSATION

METHOD 3

COMPENSATION

METHOD 2

COMPENSATION

METHOD 1

SLEW

RATE

LIMITER

CF3

CF2

CF1

COMP0

COMP7

COMP6

COMP5

COMP4

COMP3

COMP2

COMP1

DISTRIBUTOR

COMPENSATION

DESTINATIONS

COMPENSATION

METHODS

COMBINER

REFx TDCS AND

AUXILIARY TDCS

AUXILIARY DPLL

AUXILIARY NCO 0/NCO 1

DPLL0/DPLL1

Figure 120. Integrated Compensation Subsystem

AD9546/PCBZ Datasheet(PDF) 177 Page - Analog Devices

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