AD9546SLASHPCBZ datasheet(178/205 Pages) AD

178 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 178 of 205

Each compensation method produces its own compensation

factors (CF1, CF2, and CF3). The combiner translates the three

CFx factors to eight possible combined compensation factors,

COMPx, according to Table 100. The index, x, of COMPx is the

3-bit value programmed in the associated compensation

destination bit field per Figure 121.

Table 100. Composite Compensation Factor (COMPx)

COMPx Index (x)

Compensation Factor

Index

Combiner

Output

Not applicable

CF1

CF2

1, 2

CF1 × CF2

CF3

1, 3

CF1 × CF3

2, 3

CF2 × CF3

1, 2, 3

CF1 × CF2 × CF3

The distributor gives the user the ability to connect any COMPx

output from the combiner to any compensation destination.

The AD9546 implements the distributor through six 3-bit bit

fields, where each bit field corresponds to a specific

compensation destination per Figure 121. The user assigns a

COMPx factor to a specific destination by writing a 3-bit value

to the corresponding compensation destination bit field. See

the System Clock Compensation Programming Registers

section for a register programming example.

Any of the COMPx selections (except for COMP0) constitute a

real-time sequence of compensation values originating from the

various compensation sources. This real-time sequence

continuously applies to the associated compensation destination.

Because the COMPX outputs respond to the various stimuli

associated with the compensation sources, COMPx tends to

vary over time, causing the associated compensation

destination to vary accordingly. However, if the frequency

variation vs. time slope is too large, the slope can appear as an

unwanted noise source to compensation destinations employing

closed-loop compensation (such as DPLL0, DPLL1, and the

auxiliary DPLL).

To mitigate the potential noise injection caused by COMPx

exhibiting an excessive frequency variation vs. time slope, the

combiner employs programmable rate limiting via a slew rate

limiter. The slew rate limiter effectively prevents the rate of

change of frequency originating from compensation sources

from exceeding a preset limit.

The user controls rate limiting via Bits[2:0] of Register 0x0283

according to Table 101. The rate limit values are in units of

parts per million per second (ppm/sec or 10−6/sec) and

represent the maximum rate of change of COMPx that occurs

given the value of Bits[2:0]. Because rate limiting applies

globally to COMP1 through COMP7, the user must base the rate

limit selection on the stability requirements of the most

frequency sensitive compensation destination.

Table 101. Compensation Rate Limiting

Bits[2:0] (Binary)

Rate Limit (ppm/sec)

000

None

001

0.715

010

1.430

011

2.860

100

5.720

101

11.44

110

22.88

111

45.76

Compensation Assignment Guidelines

When using a UTSP (see the User Time Stamp Processor

(UTSP) section) with an auxiliary NCO selected as the time

scale, both the auxiliary NCO and the UTSP time stamp source

must use the same COMPx factor. That is, the user must

program identical values in the bit field of the REFx or auxiliary

REFx TDC compensation destination and in the bit field of the

auxiliary NCO 0 or auxiliary NCO 1 compensation destination

(whichever is the selected time scale for the UTSP). See Figure 121

for the compensation destination bit fields.

To avoid a positive feedback loop in the integrated

compensation subsystem, do not assign COMPx sources

involving CF2 in Table 100 to the following compensation

destinations:

•

DPLL0 NCO compensation destination when Bit 0 of

•

DPLL1 NCO compensation destination when Bit 0 of

Likewise, do not assign COMPx sources involving CF3 in Table 100

to the auxiliary DPLL (the reason Bit 6 of Register 0x280 is

shaded out in Figure 121).

SYSTEM CLOCK COMPENSATION PROGRAMMING

REGISTERS

System clock compensation comprises three compensation

methods and six compensation destinations. Three 8-bit

registers constitute the function of the distributor in Figure 120.

The three registers function as a connection matrix with six

3-bit bit fields distributed over the three registers (see Figure 121).

Each 3-bit bit field associates with one of the following six

compensation destinations:

•

Auxiliary DPLL

•

REFx TDCs and auxiliary REFx TDCs

•

Auxiliary NCO 0

•

Auxiliary NCO 1

•

DPLL0

•

DPLL1

AD9546/PCBZ Datasheet(PDF) 178 Page - Analog Devices

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