AS4LC2M8S1 datasheet(1/28 Pages) ALSC

No. de pieza	AS4LC2M8S1

Descripción Electrónicos	3.3V 2M x 8/1M x 16 CMOS synchronous DRAM

PDF	28 Pages

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Fabricante Electrónico	ALSC [Alliance Semiconductor Corporation]

Página de inicio	https://www.alliancememory.com

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AS4LC2M8S1

AS4LC1M16S1

7/5/00

ALLIANCE SEMICONDUCTOR

1

3.3V 2M

×××× 8/1M ×××× 16 CMOS synchronous DRAM

• PC100 functionality

• Automatic and direct precharge including concurrent

autoprecharge

• Burst read, write/Single write

• Random column address assertion in every cycle, pipelined

operation

• LVTTL compatible I/O

• 3.3V power supply

• JEDEC standard package, pinout and function

- 400 mil, 44-pin TSOP II (2M × 8)

- 400 mil, 50-pin TSOP II (1M × 16)

• Read/write data masking

• Programmable burst length (1/2/4/8/ full page)

• Programmable burst sequence (sequential/interleaved)

• Programmable CAS latency (1/2/3)

Selection guide

Symbol

–7

–8

–10

Unit

Bus frequency (CL = 3)

fMax

143

125

100

MHz

Maximum clock access time (CL = 3)

tAC

5.5

6

ns

Minimum input setup time

tS

22

2

ns

Minimum input hold time

tH

1.0

ns

Row cycle time (CL = 3, BL = 1)

tRC

70

80

ns

Maximum operating current ([

×16], RD or

WR, CL = 3), BL = 2

ICC1

130

100

mA

Maximum CMOS standby current, self refresh

ICC6

11

1

mA

Pin designation

Pin(s)

Description

DQM (2M × 8)

UDQM/LDQM (1M × 16)

Output disable/write mask

A0 to A10

Address inputs

RA0 – 10

CA0 – 7 (

×16)

CA0 – 8 (

×8)

A11

Bank address (BA)

DQ0 to DQ7 (2M

× 8)

DQ0 to DQ15 (1M

× 16)

Input/output

RAS

Row address strobe

CAS

Column address strobe

WE

Write enable

CS

Chip select

VCC, VCCQ

Power (3.3V ± 0.3V)

VSS, VSSQ

Ground

CLK

Clock input

CKE

Clock enable

Pin arrangement

VCC

DQ0

DQ1

VSSQ

DQ2

DQ3

VCCQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VCCQ

LDQM

WE

VSS

DQ15

DQ14

VSSQ

DQ13

DQ12

VCCQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VCCQ

NC

UDQM

CLK

CKE

NC

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

TSOP II

23

24

25

28

27

26

CAS

RAS

CS

A11

A10

A0

A1

A2

A3

VCC

A9

A8

A7

A6

A5

A4

VSS

VCC

DQ0

VSSQ

DQ1

VCCQ

DQ2

VSSQ

DQ3

VCCQ

NC

WE

CAS

RAS

CS

A11

A10

A0

A1

A2

A3

VCC

VSS

DQ7

VSSQ

DQ6

VCCQ

DQ5

VSSQ

DQ4

VCCQ

NC

DQM

CLK

CKE

NC

A9

A8

A7

A6

A5

A4

VSS

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

TSOP II

Features

•Organization

- 1,048,576 words × 8 bits × 2 banks (2M × 8)

11 row, 9 column address

- 524,288 words × 16 bits × 2 banks (1M × 16)

11 row,8 column address

• All signals referenced to positive edge of clock, fully

synchronous

• Dual internal banks controlled by A11 (bank select)

•High speed

- 143/125/100 MHz

- 7/8/10 ns clock access time

• Low power consumption

- Active:

576 mW max

- Standby: 7.2 mW max, CMOS I/O

• 2048 refresh cycles, 64 ms refresh interval

• Auto refresh and self refresh (2K self refresh mode at 64 ms)

LEGEND

2M

× 81M × 16

Configuration

1M

× 8 × 2 banks

512K

× 16 × 2 banks

Refresh Count

2K

Row Address

2K (A0 – A10)

Bank Address

2 (BA)

Column Address

512 (A0 – A8)

256 (A0 – A7)

Número de pieza similar - AS4LC2M8S1

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Alliance Semiconductor ...	AS4LC2M8S1	721Kb / 29P	3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM
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	AS4LC2M8S1-8TC	721Kb / 29P	3.3V 2M 횞 8/1M 횞 16 CMOS synchronous DRAM

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