FXLS8964AF datasheet(40/98 Pages) NXP

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NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

40 / 98

Table 23. VECM_LSB register (address 02h) bit allocation

Bit

Name

VECM[7:0]

Reset

Access

Table 24. VECM_LSB register (address 02h) bit description

Field

Description

7:0

VECM[7:0]

LSB of the 12-bit unsigned acceleration vector modulus result

13.4 VECM_MSB register (address 03h)

This register contains the MSB of the 12-bit, unsigned vector magnitude

result (acceleration vector modulus); The result is only calculated when

SENS_CONFIG5[VECM_EN] = 1. Note that whenever the VECM_LSB or VECM_MSB

registers are read the SRC_DRDY event flag is also cleared. The endianness of the

vector magnitude output data is programmable via

SENS_CONFIG2[LE_BE] and

defaults to little-endian mode.

Table 25. VECM_MSB register (address 03h) bit allocation

Bit

Name

—

VECM[11:8]

Reset

Access

Table 26. VECM_MSB register (address 03h) bit description

Field

Description

3:0

VECM[11:8]

MSB of the 12-bit unsigned acceleration vector modulus result

13.5 OUT_X_LSB, OUT_X_MSB, OUT_Y_LSB, OUT_Y_MSB, OUT_Z_LSB,

OUT_Z_MSB registers (addresses 04h to 09h)

These registers contain the 12-bit X-axis, Y-axis, and Z-axis output acceleration data in

2's complement format.

The output data is latched into the

OUT_X/Y/Z registers along with the assertion of the

SRC_DRDY event flag.

When

SENS_CONFIG2[F_READ] = 1, the auto-increment mechanism will skip the MSB

registers in a burst read transaction. This will shorten the output data size from 6 bytes to

3 bytes per XYZ sample read.

The endianness of the output data is programmable via

SENS_CONFIG2[LE_BE] and

defaults to little-endian mode.

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