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FXLS8964AF Datasheet(PDF) 65 Page - NXP Semiconductors

No. de pieza FXLS8964AF
Descripción Electrónicos  3-Axis Low-g Accelerometer
PDF  98 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8964AF Datasheet(HTML) 65 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8964AF
3-Axis Low-g Accelerometer
FXLS8964AF
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Objective data sheet
Rev. 2 — 30 October 2020
65 / 98
Table 74. OFF_X register (addresses 22h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
OFF_X[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 75. OFF_Y register (addresses 23h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
OFF_Y[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 76. OFF_Z register (addresses 24h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
OFF_Z[7:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
13.24 BUF_CONFIG1 register (address 26h)
The BUF_CONFIG1 register controls the output buffer read order, data collection mode
and trigger event sources.
Table 77. BUF_CONFIG1 register (address 26h) bit allocation
Bit
7
6
5
4
3
2
1
0
Name
BUF_TYPE
BUF_MODE[1:0]
BUF_GATE
TRIG_
SDCD_WT
TRIG_
SDCD_OT
—
TRIG_
ORIENT
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 78. BUF_CONFIG1 register (address 26h) bit description
Field
Description
BUF_TYPE
Buffer data read out order:
0: First In First Out (FIFO). Default
In FIFO mode, the oldest sample data is read out first, followed by the more recent
sample data.
1: First In Last Out (LIFO).
In LIFO mode, the newest data sample is read out first, followed by the older sample data.
Note: It is not possible to change the buffer operating mode without first clearing the
SENS_CONFIG1[ACTIVE] and SENS_CONFIG4[INT2_FUNC] bits.



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