UPD765B datasheet(2/17 Pages) NEC

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uPD765A/uPD765B

NEC

Pin Identification

No.

Symbol

RESET

6-13

DB0-DB7

DRQ

DACK

INDEX

Function

Reset input

Read control input

Write control input

Chip select input

Data or status select input

Bidirectional data bus

DMA request output

DMA acknowledge input

Terminal count input

Index input

INT

CLK

GND

WCLK

WINDOW

R DATA

SYNC

MFM

SIDE

28 29

USn US1

Interrupt request output

Clock input

Ground

Write clock input

Read data window input

Read data input

VCO sync output

Write enable output

MFM output

Head select output

FDD unit select output

WDATA

31, 32

P S 0 PS1

FLT/TRK0

WPRT/2SIDE

3 5

READY

HDLD

FLTR/STEP

LCT/DIR

m/SEEK

Write data output

Preshift

output

Fault/track zero input

Write protect/two side

input

Ready input

Head load output

Fault reset/step output

Low current direction

output

Read/write/ seek output

DC power ( +5 V)

Pin Functions

RESET (Reset)

INT (Interrupt)

The RESET input places the FDC in the idle state. It re-

sets the output lines to the FDD to 0 (low), except PSO, 1

and WDATA (undefined), INT and DRQ also go low;

DBO-7 goes to an input state. It does not affect SRT,

HUT, or HLT in the Specify command. If the RDY input is

held high during reset, the FDC will generate an inter-

rupt within 1.024ms.

To clear this interrupt, use the

Sense Interrupt Status command.

The INT output is FDC’s interrupt request. In Non-DMA

mode, the signal is output for each byte. In DMA mode,

it is output at the termination of a command operation.

CLK (Clock)

CLK is the input for the FDC’s single-phase, lTL-level

squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up

resistor.)

RD (Read Strobe)

The RD input allows the transfer of data from the FDC

to the data bus when low and either C

Sor DACK is

asserted.

WR (Write Strobe)

TheWR

input allows the transfer of data to the FDC

from the data bus when low. Disabled when C

Sis high.

A0 (Data/Status Select)

The A0 input selects the data register (A0 = 1) or status

data bus.

S(Chip Select)

The FDC is selected when C

Sis low, enabling RD and

WR.

DBo-DB7 (Data Bus)

DBo-DB7 are a bidirectional 8-bit

data bus. Disabled

when C

Sis high.

DRQ (DMA Request)

The FDC asserts the DRQ output high to request a DMA

transfer.

DACK (DMA Acknowledge)

When the DACK input is low, a DMA cycle is active and

the controller is performing a DMA transfer.

TC (Terminal Count)

When theTC input is high, it indicates the termination of

a DMA transfer. It terminates data transfer during Read/

Write/Scan commands in DMA or interrupt mode.

INDEX (Index)

The INDEX input goes high at the beginning of a disk

track.

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