UPD765B datasheet(9/17 Pages) NEC

9 / 17 page

NEC

uPD765A/uPD765B

liming Waveforms (Cont)

Write Clock

Index

INDEX

Internal

Registers

The uPD765A/uPD765B

contains two registers which

may be accessed by the main system processor: a sta-

tus register and a data register. The 8-bit

main status

may be accessed at any time. The 8-bit

data register

(which actually consists of four registers, STO-ST3,

in a

stack with only one register presented to the data bus at

a time), stores data, commands, parameters, and FDD

status information. Data bytes are read out of, or written

into, the data register in order to program or obtain the

results after a particular command (table 3). Only the

status register may be read and used to facilitate the

transfer of data between the processor and uPD765A/

uPD765B.

The relationship between the status/data registers and

the signals RD, WR, and A0 is shown in table 1.

Table 1. Status/Data Register Addressing

Function

Read main status register

Illegal

Read from data register

Write into data register

The bits in the main status register are defined in

table 2.

Table 2. Main Status Register

No.

Name

Function

DB0

D0B

(FDD 0 Busy)

FDD number 0 is in the seek mode. II any

of the DnB bits IS set FDC will not accept

read or write command.

DB1

D1B

(FDD 1 Busy)

FDD number1 is in the seek mode. If any of

the DnB bits IS set FDC will not accept read

or write command.

DB2

D2B

(FDD 2 Busy)

FDD number 2 is in the seek mode If any

of the DnB bits IS set FDC will not acceot

DB3

D3B

read or write command

(FDD 3 Busy)

FDD number 3 is in the seek mode. If any

of the DnB bits IS set FDC will not accept

read or write command

DB4

A Read or Write command is in orocess.

(FDC Busy)

FDC will not accept any other command.

DB5

EXM

This bit is set only during execution

ohase

(Execution

Mode)

in non-DMA mode When DB5 goes low,

execution phase has ended and result

phase has started. It operates only during

non-DMA mode of operation

DIO

Indicates direction of data transfer be-

(Data Input/Output) tween FDC and data regrster If DIO=1,

then transfer is from data register to the

processor. If DIO = 0, then transfer is from

the processor to data register.

RQM

Indicates

data register IS ready to send or

(Request for Master)

receive data to or from the processor Both

bits DIO and RQM should be used to per-

form

the

hand-shaking

functions

“ready” and “directron” to the processor

The DIO and RQM bits in the status register indicate

when data is ready and in which direction data will be

transferred on the data bus. See figure 1.

Figure 1.

DIO and RQM

Data

In/Out

(DIO)

Out

FDC

and

Into

Processor

Out Processor and Into FDC

5-l 1

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