NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Preliminary 01 / 2002
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
200pin One Bank Unbuffered DDR SO-DIMM Based on DDR266/200 32Mx8 SDRAM
Features
• JEDEC Standard 200-Pin Small Outline Dual In-Line Memory
Module (SO-DIMM)
• 32Mx64 Double Unbuffered DDR SO-DIMM based on 32Mx8
DDR SDRAM.
• Performance :
PC1600
PC2100
Speed Sort
- 8B
- 75B
- 7K
DIMM CAS Latency
2
2.5
2
Unit
f CK Clock Frequency
100
133
133
MHz
t CK Clock Cycle
10
7.5
7.5
ns
f DQ DQ Burst Frequency
200
266
266
MHz
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
• Data is read or written on both clock edges
• DRAM DLL aligns DQ and DQS transitions with clock
transitions.
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/10/2 Addressing (row/column/bank)
• 7.8
µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
Description
NT256D64S88A2GM is an unbuffered 200-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 32Mx64 module is a single-bank DIMM that uses eight 32Mx8 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 200pin DDR SO-DIMMs provide a high-performance, flexible 8-byte interface in a 2.66” long space-saving footprint.
Ordering Information
Part Number
Speed
Organization
Leads
Power
143MHz (7ns @ CL = 2.5 )
NT256D64S88A2GM-7K
133MHz (7.5ns @ CL= 2 )
PC2100
133MHz (7.5ns @ CL= 2.5 )
NT256D64S88A2GM-75B
100MHz (10ns @ CL = 2 )
PC2100
125MHz (8ns @ CL = 2.5 )
NT256D64S88A2GM-8B
100MHz (10ns @ CL = 2 )
PC1600
32Mx64
Gold
2.5V
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