NT256D64S88A2GM datasheet(10/14 Pages) ETC1

10 / 14 page

NT256D64S88A2GM

256MB : 32M x 64

PC2100 / PC1600 Unbuffered DDR SO-DIMM

Preliminary 01 / 2002

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Operating, Standby, and Refresh Currents

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

Parameter/Condition

PC1600

PC2100

Unit

Notes

I DD0

Operating Current : one bank; active / precharge; tRC = tRC (MIN) ;

tCK = tCK (MIN) ; DQ, DM, and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

600

680

1,2

I DD1

Operating Current : one bank; active / read / precharge; Burst = 2;

tRC = tRC (MIN) ; CL=2.5; tCK = tCK (MIN) ; IOUT = 0mA;

address and control inputs changing once per clock cycle

720

880

1,2

I DD2P

Precharge Power-Down Standby Current :

all banks idle; power-down mode; CKE

≤ VIL (MAX) ; tCK = tCK (MIN)

120

1,2

I DD2N

Idle Standby Current : CS

≥ VIH (MIN) ; all banks idle; CKE ≥ VIH(MIN) ;

tCK = tCK (MIN) ; address and control inputs changing once per clock cycle

240

280

1,2

I DD3P

Active Power-Down Standby Current : one bank active;

power-down mode; CKE

≤ VIL (MAX) ; tCK = tCK (MIN)

120

1,2

I DD3N

Active Standby Current : one bank; active / precharge; CS

≥ VIH (MIN) ;

CKE

≥ VIH (MIN) ; tRC = tRAS (MAX) ; tCK = tCK (MIN) ; DQ, DM, and DQS

inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

400

480

1,2

I DD4R

Operating Current : one bank; Burst = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS outputs changing twice per clock cycle; CL = 2.5;

tCK = tCK (MIN) ; IOUT = 0mA

1040

1320

1,2

I DD4W

Operating Current : one bank; Burst = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

DQ and DQS inputs changing twice per clock cycle; CL=2.5;

tCK = tCK (MIN)

920

1200

1,2

t RC = t RFC (MIN)

1280

1360

1,2

I DD5

Auto-Refresh Current :

t RC = 7.8

µs

132

1,2,4

I DD6

Self-Refresh Current : CKE

≤ ?0.2V

1,2,3

1. I DD specifications are tested after the device is properly initialized.

2. Input slew rate = 1V/ ns .

3. Enables on-chip refresh and address counters.

4. Current at 7.8 µs is time averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 µs.

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