NT256D64S88A2GM
256MB : 32M x 64
PC2100 / PC1600 Unbuffered DDR SO-DIMM
Preliminary 01 / 2002
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2
SPD Entry Value
Serial PD Data Entry (Hexadecimal)
Note
Byte
Description
DDR266A
-7K
DDR266B
-75B
DDR200
-8B
DDR266A
-7K
DDR266B
-75
DDR200
-8B
0
Number of Serial PD Bytes Written during
Production
128
80
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM DDR
07
3
Number of Row Addresses on Assembly
13
0D
4
Number of Column Addresses on Assembly
10
0A
5
Number of DIMM Bank
1
01
6.
Data Width of Assembly
X64
40
7
Data Width of Assembly (cont’)
X64
00
8
Voltage Interface Level of this Assembly
SSTL 2.5V
04
9
DDR SDRAM Device Cycle Time at CL=2.5
7ns
7.5ns
8ns
70
75
80
10
DDR SDRAM Device Access Time from
Clock at CL=2.5
0.75ns
0.75ns
0.8ns
75
75
80
11
DIMM Configuration Type
Non-Parity
00
12
Refresh Rate/Type
SR/1x(7.8us)
82
13
Primary DDR SDRAM Width
X8
08
14
Error Checking DDR SDRAM Device Width
N/A
00
15
DDR SDRAM Device Attr: Min CLk Delay,
Random Col Access
1 Clock
01
16
DDR SDRAM Device Attributes:
Burst Length Supported
2,4,8
0E
17
DDR SDRAM Device Attributes: Number of
Device Banks
4
04
18
DDR SDRAM Device Attributes: CAS
Latencies Supported
2/2.5
2/2.5
2/2.5
0C
0C
0C
19
DDR SDRAM Device Attributes: CS Latency
0
01
20
DDR SDRAM Device Attributes: WE Latency
1
02
21
DDR SDRAM Device Attributes:
Differential Clock
20
22
DDR SDRAM Device Attributes: General
+/-0.2V Voltage Tolerance
00
23
Minimum Clock Cycle at CL=2
7.5ns
10ns
10ns
75
A0
A0
24
Maximum Data Access Time from Clock at
CL=2
0.75ns
0.75ns
0.8ns
75
75
80
25
Minimum Clock Cycle Time at CL=1
N/A
00
26
Maximum Data Access Time from Clock at
CL=1
N/A
00
27
Minimum Row Precharge Time(tRP)
20ns
20ns
20ns
50
50
50
28
Minimum Row Active to Row Active delay
(tRRD)
15ns
15ns
15ns
3C
3C
3C
29
Minimum RAS to CAS delay (tRCD)
20ns
20ns
20ns
50
50
50
30
Minimum RAS Pulse Width (tRAS)
45ns
45ns
50ns
2D
2D
32
31
Module Bank Density
256MB
40
32
Address and Command Setup Time Before
Clock
0.9ns
0.9ns
1.1ns
90
90
B0
33
Address and Command Hold Time After
Clock
0.9ns
0.9ns
1.1ns
90
90
B0
34
Data Input Setup Time Before Clock
0.5ns
0.5ns
0.6ns
50
50
60
35
Data Input Hold Time After Clock
0.5ns
0.5ns
0.6ns
50
50
60
36-61
Reserved
Undefined
00
62
SPD Revision
Initial
Initial
Initial
00
00
00
63
Checksum Data
8F
BF
45
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