AT25PE80 datasheet(8/63 Pages) DIALOG

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AT25PE80

DS-25PE80-141C–8/2018

Read Commands

By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data

buffers. The DataFlash-L supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25., Detailed Bit-level

Read Waveforms: RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for each

mode.

5.1

Continuous Array Read (Legacy Command: E8h Opcode)

By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to

sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing

information or control signals need to be provided. The DataFlash-L incorporates an internal address counter that will

automatically increment on every clock cycle, allowing one continuous read from memory to be performed without the

need for additional address sequences. To perform a Continuous Array Read using the optional DataFlash-L page size

(264 bytes), an opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit

page and byte address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 21-bit address sequence

specify which page of the main memory array to read and the last 9 (BA8 - BA0) of the 21-bit address sequence specify

the starting byte address within the page. To perform a Continuous Array Read using the default page size

(256 bytes), an opcode of E8h must be clocked into the device followed by three address bytes and four dummy bytes.

The first 12 bits (A19 - A8) of the 20-bit address sequence specify which page of the main memory array to read and the

last 8 bits (A7 - A0) of the 20-bit address sequence specify the starting byte address within the page. The dummy bytes

that follow the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock

pulses on the SCK pin will result in data being output on the SO (serial output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of

data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue

reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from

the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the

device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no

delays will be incurred when wrapping around from the end of the array to the beginning of the array.

A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum

SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read

bypasses the data buffers and leaves the contents of the buffers unchanged.

Warning:

This command is not recommended for new designs.

5.2

Continuous Array Read (High Frequency Mode: 1Bh Opcode)

This command can be used to read the main memory array sequentially at the highest possible operating clock

frequency up to the maximum specified by f

CAR4. To perform a Continuous Array Read using the optional DataFlash-L

page size (264 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked into the device

followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 21-bit address sequence

specify which page of the main memory array to read and the last 9 bits (BA8 - BA0) of the 21-bit address sequence

specify the starting byte address within the page. To perform a Continuous Array Read using the default page size (256

bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A19 - A0) and two dummy

bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO

(Serial Output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of

data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue

reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover

from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read,

the device will continue reading back at the beginning of the first page of memory. As with crossing over page

boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.

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