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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

49 of 113

Table 41: I2C Interface Configuration

I2C_HIZ_EN

0x0015 [0]

Ship Mode

Hi-Z Mode

Active Battery Mode

Charge Mode

disabled

active

disabled

active

I2C communication uses the SDA and SCL are open drain I/O pins. Pull these up to VDDIO with a

1 k

Ω to 100 kΩ resistor. SCL is the serial clock generated by the host and SDA is the serial address

and data input/output.

DA9072 is compatible with the standard I2C protocol but only operates as a slave. The I2C bus

supports a frequency range of 400 kHz (Fast mode) to 100 kHz (Slow mode). The transfer protocol is

the same whether operating in Fast or Slow mode.

The device supports 8-bit addressing only. The I2C slave ID is 7-bit and can be set at register 0x0040

[6:0], with a range of 00 to 7F.

When active, the I2C bus is monitored at all times for a valid SLAVE address, and an

ACKNOWLEDGE (ACK) bit is generated if the SLAVE address is true.

This indicates to the master that the communication link has been established. The master then

generates SCL clock cycles to transmit or receive data. After receiving data, an ACK is generated

either by the DA9072 or the master. Basic communication is described below and in Figure 32.

● A START condition is initiated by a high to low transition on the SDA line while the SCL is in the

high state

● A STOP condition is indicated by a low to high transition on the SDA line while the SCL is in the

high state

● An ACK is indicated by the receiver pulling the SDA line low during the following clock cycle

SDA

SCL

Data SDA must be stable

during high part of clock

SCL

Data sampled on SCL

rising edge and driven on

SCL falling edge

Start ( S ) is SDA falling while

SCL high

Stop (P ) is SDA rising while

SCL high

Figure 32: I2C Start and Stop Conditions

Each data sequence is 9-bit, consisting of 8-bit data and 1-bit ACK. Data sequences can be repeated

indefinitely. At the end of the data transfer, the master generates a STOP condition.

The bus returns to IDLE if during a message a new START or STOP condition occurs. Data is

transmitted as MSB first for both READ and WRITE operations.

4.9

Buck Regulator

DA9072 includes a nano-ampere quiescent current buck regulator with adjustable output voltage, up

to 300 mA load capability, and Power Saving mode for excellent efficiency at light load. It also

features dynamic voltage scaling (DVS) capability and multiple protection features.

4.9.1

Buck Output Voltage Programmability

The DA9072 buck regulator output voltage is programmable in 50 mV steps between 0.6 V and

2.1 V. The output voltage is set by BUCK_VOUT (register 0x0030 [4:0]). The voltage can be set

within two ranges based on the value of the VOUT_RANGE_HI bit (register 0x0030 [6]). The output

voltage can be changed within one of the two range settings while the buck is enabled (0.6 V to 1.3 V

or 1.3 V to 2.1 V). The range setting, however, can only be changed while the buck is disabled.

DA9072 Datasheet(PDF) 49 Page - Dialog Semiconductor

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