DA9072 datasheet(53/113 Pages) DIALOG

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DA9072

Ultra-Low Quiescent Current PMIC

Datasheet

Revision 3.0

14-Jun-2021

CFR0011-120-00

53 of 113

The first priority is to reduce and isolate high frequency switching noise so that it does not disturb

sensitive nodes. For the buck regulator, the primary sources of noise are at the input capacitor

ground and VDD_BUCK nodes. Connect the input capacitor as close as possible to the

PGND_BUCK and VDD_BUCK pins. This reduces the parasitic inductance responsible for many of

the voltage spikes during switching. Route the current carrying traces (VDD_BUCK, PGND, VOUT)

directly to the pads of all capacitors, not through vias or separate traces. This applies to both input

and output capacitors and is good practice in general. Where possible these current carrying traces

should be wide or large copper areas to reduce impedance and improve thermal resistance. Route

these traces on the top layer only. Connect VDD_SYS and VDD_BUCK close to, or at, the pins to

further reduce impedance.

The second largest noise sources are the SW nodes. Although the current here is not switching, the

fast voltage swings can introduce noise through capacitive coupling. To reduce this, use the smallest

area possible for the SW nodes, while keeping in mind the current handling requirements.

SW_BUCK should be routed on the second layer with multiple vias, which allows the best routing for

the buck input caps. As much as possible, surround the SW nodes with GND copper to help shield

the nearby FB traces.

Route all signal traces such as FB, SDA, and SCL away from the SW nodes, buck input caps, and

the inductor. Shield these sensitive traces with GND copper or route on a lower layer with a ground

plane to provide shielding.

To create a good shield, flood one inner layer with copper and connected as a common ground to the

GND pins of the IC (A1, D3, E1, F2, F3, and F4) and external GND connections. Layer 2 is

recommended. Connect PGND_BUCK directly to the buck input cap before connecting to the ground

plane. Multiple ground planes, for example a mid-layer and bottom layer plane, are helpful to control

high frequency noise and improve thermal performance.

Important: Do not use the AGND node as a ground plane. Instead, connect all AGNDs to a small

area or by star connection to the AGND pin. Connect the AGND pin to the larger ground plane in a

quiet location.

For an example of top and second layer routing, see Figure 33 and Figure 34. The buck input cap is

C21. The cap is placed close to the IC with no vias between the pin and the cap. C23 is the buck

output cap, connected on the top layer. L20 is the buck inductor; its SW node is routed on layer 2

and connected by multiple vias.

Layer-2 is a mostly filled GND plane, which provides shielding around the SW nodes routed on this

layer. The isolated AGND area is on the right side of Figure 34. AGND is connected to the GND area

at a single point on another layer, not shown here.

Note 1

Figure 33 and Figure 34 are the PCB layout of DA9073. For DA9072, L30 and the SW node area on

layer-2 can be removed and filled with GND plane.

DA9072 Datasheet(PDF) 53 Page - Dialog Semiconductor

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