UCC28C53_V01 datasheet(30/48 Pages) TI

30 / 48 page

9.2.2.9 Start-Up Circuit

At start-up, the IC gets its power directly from the high-voltage bulk, through a high-voltage resistor (RSTART).

The selection of the start-up resistor is the tradeoff between power loss and start-up time. The current flowing

through RSTART at the minimum input voltage must be higher than the VDD current under UVLO conditions (100

µA at its maximum value). A resistance of 420-kΩ was chosen for RSTART, providing 250 µA of start-up current

at low-line conditions. The start-up resistor is physically comprised of two 210-kΩ resistors in series to meet the

high voltage requirements and power rating at high-line.

After VDD is charged up above the UVLO-ON threshold, the UCC28C42 starts to consume full operating

current. The VDD capacitor is required to provide enough energy to prevent its voltage from dropping below

the UVLO-OFF threshold during start-up, before the output is able to reach its regulated level. A large bulk

capacitance would hold more energy but would result in slower start-up time. In this design, a 120-µF capacitor

is chosen to provide enough energy and maintain a start-up time of approximately 7 seconds. For faster start-up,

the bulk capacitor value may be decreased or the RSTART resistor modified to a lower value.

9.2.2.10 Voltage Feedback Compensation

Feedback compensation, also called closed-loop control, can reduce or eliminate steady state error, reduce

the sensitivity of the system to parametric changes, change the gain or phase of a system over some desired

frequency range, reduce the effects of small signal load disturbances and noise on system performance, and

create a stable system from an unstable system. A system is stable if its response to a perturbation is that the

perturbation eventually dies out. A peak current mode flyback uses an outer voltage feedback loop to stabilize

the converter. To adequately compensate the voltage loop, the open-loop parameters of the power stage must

be determined.

9.2.2.10.1 Power Stage Poles and Zeroes

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction

mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (LP) is greater than the

inductance for DCM or CCM boundary mode operation, called the critical inductance (LPcrit), then the converter

operates in CCM:

LP > LPcrit , then CCM

(17)

Pcrit

OUT × :NPS ;

2 × f

IN + VOUT × NPS p

(18)

For the entire input voltage range, the selected inductor has a value larger than the critical inductor. Therefore,

the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced RCS and the internal 2R/R

resistor divider which sets up the internal current sense gain, ACS = 3. The exact value of these internal resistors

is not critical but the IC provides tight control of the resistor divider ratio, so regardless of the actual resistor

value variations their relative value to each other is maintained.

The DC open-loop gain (GO) of the fixed-frequency voltage control loop of a peak current mode control CCM

flyback converter shown in Equation 19 is approximated by first using the output load (ROUT), the primary to

secondary turns ratio (NPS), and the maximum duty cycle (D) as calculated in Equation 20.

O =

OUT × NPS

CS × ACS

:1 F D;

:2 × M; + 1

(19)

In Equation 19, D is calculated with Equation 20, τL is calculated with Equation 21, and M is calculated with

Equation 22.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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