UCC28C53_V01 datasheet(33/48 Pages) TI

33 / 48 page

select a value to approximate a high-frequency short circuit, such as 10 nF, as a starting point and make

adjustments if required. The RRAMP and RCSF resistors form a voltage divider from the oscillator charge slope

and this proportional ramp is injected into the CS pin to add slope compensation. Choose the value of RRAMP to

be much larger than the RRT resistor so that it does not load down the internal oscillator and result in a frequency

shift. The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform

(VOSCpp) equal to 1.9 V, and the minimum ON time, as shown in Equation 37.

ONmin

(36)

SOSC =

VOSCpp

tONmin

1.9 V

5.7 Js

= 333

(37)

To achieve a 44.74-mV/µs compensation slope, RCSF is calculated with Equation 38. In this design, RRAMP is

selected as 24.9 kΩ, a 3.8-kΩ resistor was selected for RCSF.

CSF =

RAMP

OSC

F 1

(38)

9.2.2.10.3 Open-Loop Gain

Once the power stage poles and zeros are calculated and the slope compensation is determined, the power

stage open-loop gain and phase of the CCM flyback converter can be plotted as a function of frequency. The

power stage transfer function can be characterized with Equation 39.

HOPEN :s; = G0 ×

l1 +

s:f;

ESRz p

l1 F

s:f;

RHPz p

1 +

s:f;

1 +

s:f;

P2 × QP

s:f;2

:XP2 ;2

(39)

The bode for the open-loop gain and phase can be plotted by using Equation 40.

GainOPEN :s; = 20 × log: HOPEN :s; ;

(40)

See Figure 9-4 and Figure 9-5.

frequency (Hz)

100

1000

10000

100000

-25

-20

-15

-10

-5

D001

Figure 9-4. Converter Open-Loop Bode Plot - Gain

frequency (Hz)

100

1000

10000

100000

-180

-135

-90

-45

D002

Figure 9-5. Converter Open-Loop Bode Plot -

Phase

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