UCC28C53_V01 datasheet(38/48 Pages) TI

38 / 48 page

11 Layout

11.1 Layout Guidelines

11.1.1 Precautions

Careful layout of the printed board is a necessity for high-frequency power supplies. As the device-switching

speeds and operating frequencies increase, the layout of the converter becomes increasingly important.

This 8-pin device has only a single ground for the logic and power connections. This forces the gate-drive

current pulses to flow through the same ground that the control circuit uses for reference. Thus, the interconnect

inductance must be minimized as much as possible. One implication is to place the device (gate driver) circuitry

close to the MOSFET it is driving. This can conflict with the need for the error amplifier and the feedback path to

be away from the noise generating components.

The single most critical item in a PWM controlled printed-circuit board layout is the placement of the timing

capacitor. While both the supply and reference bypass capacitor locations are important, the timing capacitor

placement is far more critical. Any noise spikes on the CCT waveform due to lengthy printed circuit trace

inductance or pick-up noise from being in proximity to high power switching noise causes a variety of operational

problems. Dilemmas vary from incorrect operating frequency caused by pre-triggering the oscillator due to noise

spikes to frequency jumping with varying duty cycles, also caused by noise spikes. The placement of the timing

capacitor must be treated as the most important layout consideration. Keep PC traces as short as possible to

minimize added series inductance.

11.1.2 Feedback Traces

Try to run the feedback trace as far from the inductor and noisy power traces as possible. You would also like

the feedback trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but

keeping it away from EMI and other noise sources is the more critical of the two. If possible, run the feedback

trace on the side of the PCB opposite of the inductor with a ground plane separating the two.

11.1.3 Bypass Capacitors

When using a low value ceramic bypass capacitor, it must be placed as close to the VDD pin of the device

as possible. This eliminates as much trace inductance effects as possible and give the internal device rail a

cleaner voltage supply. Using surface mount capacitors also reduces lead length and lessens the chance of

noise coupling into the effective antenna created by through-hole components.

11.1.4 Compensation Components

For best stability, external compensation components must be placed close to the IC. Keep FB lead length as

short as possible and FB stray capacitance as small as possible. TI recommends surface mount components

here as well for the same reasons discussed for the filter capacitors. These must not be placed very close to

traces with high switching noise.

11.1.5 Traces and Ground Planes

Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a

standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. The inductor,

output capacitors, and output diode must be as close to each other possible. This helps reduce the EMI radiated

by the power traces due to the high switching currents through them. This also reduces lead inductance and

resistance as well, which in turn reduces noise spikes, ringing, and resistive losses that produce voltage errors.

The grounds of the IC, input capacitors, output capacitors, and output diode, if applicable, must be connected

close together directly to a ground plane. It would also be a good idea to have a ground plane on both sides

of the PCB. This reduces noise as well by reducing ground loop errors as well as by absorbing more of the

EMI radiated by the inductor. For multi-layer boards with more than two layers, a ground plane can be used

to separate the power plane, where the power traces and components are, and the signal plane, where the

feedback and compensation and components are, for improved performance. On multi-layer boards the use of

vias is required to connect traces and different planes. It is good practice to use one standard via per 200 mA of

current if the trace conducts a significant amount of current from one plane to the other.

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

www.ti.com

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