UCC28C53_V01 datasheet(31/48 Pages) TI

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D =

PS × VOUT

BULKmin

PS × VOUT ;

(20)

2 × L

P × fSW

OUT × :NPS ;

(21)

M =

OUT × NPS

BULKmin

(22)

For this design, a converter with an output voltage (VOUT) of 12 V, and 48 W relates to an output load (ROUT)

equal to 3 Ω at full load. With a maximum duty cycle of 0.627, a current sense resistance of 0.75 Ω, and a

primary to secondary turns-ratio of 10, the open-loop gain calculates to 3.082 or 9.776 dB.

A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half

plane zero (ωESRz) to the power stage, and the frequency of this zero (fESRz), are calculated with Equation 23

and Equation 24.

ESRz

ESR × COUT

(23)

ESRz =

2 × N × R

ESR × COUT

(24)

The fESRz zero for an output capacitance of 2200 µF and a total ESR of 43 mΩ is located at 1.682 kHz.

CCM flyback converters have a zero in the right-half plane (RHP) in their transfer function. A RHP zero has the

same 20 dB per decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it

adds a 90° phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency

location (fRHPz) of the RHP zero (ωRHPz) is a function of the output load, the duty cycle, the primary inductance

(LP), and the primary to secondary side turns ratio (NPS).

RHPz

OUT × :1

F D;

2 × :N

PS ;

P × D

(25)

RHPz

OUT × :1

F D;

2 × :N

PS ;

2 × N × L

P × D

(26)

The right-half plane zero frequency increases with higher input voltage and lighter load. Generally, the design

requires consideration of the worst case of the lowest right-half plane zero frequency and the converter must be

compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V

DC input, the RHP zero frequency (fRHPz) is equal to 7.07 kHz at maximum duty cycle, full load.

The power stage has one dominate pole (ωP1) which is in the region of interest, located at a lower frequency

(fP1); which is related to the duty cycle, the output load, and the output capacitance, and calculated with Equation

28. There is also a double pole placed at half the switching frequency of the converter (fP2) calculated with

Equation 30. For this example, pole fP1 is located at 40.37 Hz and fP2 is at 55 kHz.

P1 =

:1 F D;

+ 1 + D

OUT × COUT

(27)

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SLUSER8 – JUNE 2022

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UCC28C53 Datasheet(PDF) 31 Page - Texas Instruments

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