STM32F103XC datasheet(22/143 Pages) STMICROELECTRONICS

22 / 143 page

Description

STM32F103xC, STM32F103xD, STM32F103xE

22/143

DS5792 Rev 13

mode, the master clock can be output to the external DAC/CODEC at 256 times the

sampling frequency.

2.3.22

SDIO

An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System

Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD

Memory Card Specifications Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is also fully compliant with the CE-ATA digital

protocol Rev1.1.

2.3.23

Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

2.3.24

Universal serial bus (USB)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embed a USB

device peripheral compatible with the USB full-speed 12 Mbs. The USB interface

implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint

setting and suspend/resume support. The dedicated 48 MHz clock is generated from the

internal main PLL (the clock source must use a HSE crystal oscillator).

2.3.25

GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

2.3.26

ADC (analog to digital converter)

Three 12-bit analog-to-digital converters are embedded into STM32F103xC, STM32F103xD

and STM32F103xE performance line devices and each ADC shares up to 21 external

channels, performing conversions in single-shot or scan modes. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•

Simultaneous sample and hold

•

Interleaved sample and hold

•

Single shunt

STM32F103XC Datasheet(PDF) 22 Page - STMicroelectronics

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