STM32H7B3AI datasheet(152/238 Pages) STMICROELECTRONICS

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6.3.22

DAC characteristics

Table 96. DAC characteristics

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)

Unit

VDDA

Analog supply voltage

1.8

3.3

3.6

VREF+

Positive reference voltage

1.80

VDDA

VREF-

Negative reference voltage

VSSA

Resistive Load

DAC output buffer ON

connected to VSSA

kΩ

connected to VDDA

Output Impedance

DAC output buffer OFF

10.3

RBON

Output impedance sample and hold

mode, output buffer ON

DAC output buffer ON

VDD = 2.7 V

1.6

kΩ

VDD = 2.0 V

2.6

RBOFF

Output impedance sample and hold

mode, output buffer OFF

DAC output buffer OFF

VDD = 2.7 V

17.8

kΩ

VDD = 2.0 V

18.7

Capacitive Load

DAC output buffer OFF

CSH

Sample and Hold mode

0.1

µF

VDAC_OUT

Voltage on DAC_OUT output

DAC output buffer ON

0.2

VDDA

−0.2

DAC output buffer OFF

VREF+

tSETTLING

Settling time (full scale: for a 12-bit

code transition between the lowest

and the highest input codes when

DAC_OUT reaches the final value

of ±0.5LSB, ±1LSB, ±2LSB, ±4LSB,

±8LSB)

Normal mode, DAC

output buffer ON,

CL ≤ 50 pF, RL ≥ 5 kΩ

±0.5 LSB

2.05

µs

±1 LSB

1.97

±2 LSB

1.67

±4 LSB

1.66

±8 LSB

1.65

Normal mode, DAC output buffer OFF, ±1LSB

CL=10 pF

1.7

tWAKEUP(2)

Wakeup time from off state (setting the

ENx bit in the DAC Control register)

until the final value of ±1LSB is

reached

Normal mode, DAC output buffer ON,

CL ≤ 50 pF, RL = 5 kΩ

7.5

µs

Normal mode, DAC output buffer OFF,

CL ≤ 10 pF

PSRR

DC VDDA supply rejection ratio

Normal mode, DAC output buffer ON,

CL ≤ 50 pF, RL = 5 kΩ

−80

−28

tSAMP

Sampling time in Sample and Hold

mode

CL=100 nF

(code transition between the lowest

input code and the highest input code

when DAC_OUT reaches the ±1LSB

final value)

MODE<2:0>_V12=100/101

(BUFFER ON)

0.7

2.6

MODE<2:0>_V12=110

(BUFFER OFF)

11.5

18.7

MODE<2:0>_V12=111(3)

(INTERNAL BUFFER OFF)

0.3

0.6

µs

Ileak

Output leakage current

(4)

CIint

Internal sample and hold capacitor

1.8

2.2

2.6

tTRIM

Middle code offset trim time

Minimum time to verify the each code

µs

Voffset

Middle code offset for 1 trim code step

VREF+ = 3.6 V

850

µV

VREF+ = 1.8 V

425

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 152/238

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