STM32H7B3AI datasheet(148/238 Pages) STMICROELECTRONICS

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Resolution

RAIN (Ω)

Minimum sampling time (s)

Direct channels(1)(2)

Fast channels(1)(3)

Slow channels(1)(4)

8 bits

100

4.10E-08

5.83E-08

9.22E-08

150

5.06E-08

6.76E-08

9.95E-08

220

6.61E-08

8.22E-08

1.11E-07

330

9.17E-08

1.08E-07

1.32E-07

470

1.24E-07

1.40E-07

1.63E-07

680

1.74E-07

1.91E-07

2.12E-07

1000

2.53E-07

2.70E-07

2.85E-07

1500

3.73E-07

3.93E-07

4.05E-07

2200

5.39E-07

5.67E-07

5.75E-07

3300

8.02E-07

8.36E-07

8.38E-07

4700

1.13E-06

1.18E-06

6800

1.62E-06

1.69E-06

1.68E-06

10000

2.36E-06

2.47E-06

2.45E-06

15000

3.50E-06

3.69E-06

3.65E-06

1. Guaranteed by design.

2. Direct channels are connected to analog I/Os (PA0_C, PA1_C, PC2_C and PC3_C) to optimize ADC performance.

3. Fast channels correspond for ADCx_INPx to PA6, PB1, PC4, PF11, PF13 and for ADCx_INNx to PA7, PB0, PC5, PF12, PF14

4. Slow channels correspond to all ADC inputs except for the Direct and Fast channels.

Figure 54. ADC conversion timing diagram

CLK

1. The sampling time defines the minimum sampling clock cycles (SMP) to be programmed in the ADC (refer to the product reference manual for details).

Sampling(1)

Mux

Number of CLK clock cycles = ADC resolution / 2

Total conversion time: 0.5 +Tsamp + N/2

SMP

1/2

Table 95. ADC accuracy

Data guaranteed by characterization for BGA packages. The values for LQFP packages might differ. ADC DC accuracy values are measured

after internal calibration.

Symbol

Parameter

Conditions(1)

Min

Typ

Max

Unit

Total undadjusted error

Direct channel

Single ended

+10/–20

LSB

Differential

±15

Fast channel

Single ended

+10/–20

Differential

±15

Slow channel

Single ended

±10

Differential

±10

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 148/238

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