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STM32H7B3AI Datasheet(PDF) 174 Page - STMicroelectronics

No. de pieza STM32H7B3AI
Descripción Electrónicos  32-bit Arm® Cortex®-M7 280 MHz MCUs, 2-Mbyte flash memory, 1.4-Mbyte RAM, 46 com. and analog interfaces, SMPS, crypto
PDF  238 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
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STM32H7B3AI Datasheet(HTML) 174 Page - STMicroelectronics

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•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS0
Note:
At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote
when applicable.
Refer to Section 6.3.16 I/O port characteristics for more details on the input/output alternate function
characteristics (CK,SD,WS).
Table 119. I2S dynamic characteristics
Symbol
Parameter
Conditions
Min(1)
Max(1)(2)
Unit
fMCK
I2S main clock output
-
-
50
MHz
fCK
I2S clock frequency
Master Tx
-
50/33(3)
MHz
Master Rx
-
40
Slave Tx
-
31/18.5(3)
Slave Rx
-
50
tv(WS)
WS valid time
Master mode
-
5.5
ns
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
2
-
th(WS)
WS hold time
Slave mode
1
-
tsu(SD_MR)
Data input setup time
Master receiver
2
-
tsu(SD_SR)
Slave receiver
2
-
th(SD_MR)
Data input hold time
Master receiver
4.5
-
th(SD_SR)
Slave receiver
1
-
tv(SD_ST)
Data output valid time
Slave transmitter (after enable edge)
-
16/27(3)
tv(SD_MT)
Master transmitter (after enable edge)
-
4/15(3)
th(SD_ST)
Data output hold time
Slave transmitter (after enable edge)
7
-
th(SD_MT)
Master transmitter (after enable edge)
0
-
1. Guaranteed by characterization results.
2. At VOS1, these values are degraded by up to 5 %.
3. Using PC3_C / PC2_C (not available on all packages).
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 174/238



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