STM32H7B3AI datasheet(171/238 Pages) STMICROELECTRONICS

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Figure 67. USART timing diagram in Slave mode

MSv65387V1

NSS

input

CPHA=0

CPOL=0

CPHA=0

CPOL=1

TX output

RX input

tsu(RX)

th(RX)

tw(SCKL)

tw(SCKH)

tc(SCK)

tr(SCK)

th(NSS)

tdis(TX)

tsu(NSS)

ta(TX)

tv(TX)

Next bits IN

Last bit OUT

First bit IN

First bit OUT

Next bits OUT

th(TX)

tf(SCK)

Last bit IN

6.3.36.3

SPI interface characteristics

Unless otherwise specified, the parameters given in Table 118 for SPI are derived from tests performed under

the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22. General

operating conditions and Section 6.3.1 , with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

Note:

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote

when applicable.

Refer to Section 6.3.16 I/O port characteristics for more details on the input/output alternate function

characteristics (SS, SCK, MOSI, MISO for SPI).

Table 118. SPI dynamic characteristics

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)(2)

Unit

fSCK

SPI clock frequency

Master mode 2.7 < VDD< 3.6 V, SPI1, 2, 3

125/100(3)

MHz

Master mode, 2.7 < VDD<3.6 V, SPI4, 5, 6

100

Master mode, 1.62 < VDD < 3.6 V, SPI4, 5, 6

75/38(3)

Slave receiver mode, 1.62 < VDD < 3.6 V

100

Slave mode transmitter/full duplex, 2.7 < VDD < 3.6 V

45/31(3)

Slave mode transmitter/full duplex, 1.62 <VDD < 3.6 V

29/18(3)

tsu(SS)

SS setup time

Slave mode

th(SS)

SS hold time

Slave mode

tsu(MI)

Data input setup time

Master mode

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 171/238

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