WM8746

Production Data

w

March 2006, PD Rev 4.0

18

POWERDOWN MODE

mode. All trace of the previous input samples is removed, but all control register settings are

preserved. When PWDN is cleared again the first 16 input samples will be ignored as the FIR will

repeat it's power-on initialisation sequence.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

2

PWDN

0

Power Down Mode Select:

0 : Normal Mode

1: Power Down Mode

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and

right channels for all three pairs of DACs from the next audio input sample. No update to the

attenuation registers is required for ATC to take effect.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

3

ATC

0

Attenuator Control Mode:

0 : Right channels use Right

attenuations

1:

Right Channels use Left

Attenuations

DAC OUTPUT CONTROL

The DAC output control word determines how the left and right inputs to the audio Interface are

applied to the left and right DACs:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PL[3:0]

Left

Output

Right

Output

0000

Mute

Mute

0001

Left

Mute

0010

Right

Mute

0011

(L+R)/2

Mute

0100

Mute

Left

0101

Left

Left

0110

Right

Left

0111

(L+R)/2

Left

1000

Mute

Right

1001

Left

Right

1010

Right

Right

1011

(L+R)/2

Right

1100

Mute

(L+R)/2

1101

Left

(L+R)/2

1110

Right

(L+R)/2

0000010

DAC Control

8:5

PL[3:0]

1001

1111

(L+R)/2

(L+R)/2

Table 6 Input to Output Control